From e55cbf26ea5ff56a80a55b38e3964ee13a5cfeff Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Tue, 27 Nov 2018 08:57:13 +0100 Subject: [PATCH] intel/compiler: fix register allocation in opt_peephole_sel This wasn't handling 64-bit cases properly. Found by inspection. Reviewed-by: Ian Romanick --- src/intel/compiler/brw_fs_sel_peephole.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_sel_peephole.cpp b/src/intel/compiler/brw_fs_sel_peephole.cpp index fd02792bebc..6395b409b7c 100644 --- a/src/intel/compiler/brw_fs_sel_peephole.cpp +++ b/src/intel/compiler/brw_fs_sel_peephole.cpp @@ -198,8 +198,7 @@ fs_visitor::opt_peephole_sel() */ fs_reg src0(then_mov[i]->src[0]); if (src0.file == IMM) { - src0 = vgrf(glsl_type::float_type); - src0.type = then_mov[i]->src[0].type; + src0 = ibld.vgrf(then_mov[i]->src[0].type); ibld.MOV(src0, then_mov[i]->src[0]); } -- 2.30.2