From e5737331ec504bb26e364e7d18dbe2d5e204f5a6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 17 Jun 2013 23:33:57 +0200 Subject: [PATCH] lasmicon: add FIFO at bankmachine input to ease timing --- milkymist/lasmicon/__init__.py | 5 +++-- milkymist/lasmicon/bankmachine.py | 32 ++++++++++++++++++++++--------- top.py | 2 +- 3 files changed, 27 insertions(+), 12 deletions(-) diff --git a/milkymist/lasmicon/__init__.py b/milkymist/lasmicon/__init__.py index adf2423b..08d647e2 100644 --- a/milkymist/lasmicon/__init__.py +++ b/milkymist/lasmicon/__init__.py @@ -20,7 +20,7 @@ class GeomSettings: self.mux_a = max(row_a, col_a) class TimingSettings: - def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, CL, read_latency, write_latency, read_time, write_time): + def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, read_latency, write_latency, req_queue_size, read_time, write_time): self.tRP = tRP self.tRCD = tRCD self.tWR = tWR @@ -28,10 +28,10 @@ class TimingSettings: self.tREFI = tREFI self.tRFC = tRFC - self.CL = CL self.read_latency = read_latency self.write_latency = write_latency + self.req_queue_size = req_queue_size self.read_time = read_time self.write_time = write_time @@ -48,6 +48,7 @@ class LASMIcon(Module): aw=geom_settings.row_a + geom_settings.col_a - address_align, dw=phy_settings.dfi_d*phy_settings.nphases, nbanks=2**geom_settings.bank_a, + req_queue_size=timing_settings.req_queue_size, read_latency=timing_settings.read_latency+1, write_latency=timing_settings.write_latency+1) self.nrowbits = geom_settings.col_a - address_align diff --git a/milkymist/lasmicon/bankmachine.py b/milkymist/lasmicon/bankmachine.py index ce0a2b3b..7f05edd7 100644 --- a/milkymist/lasmicon/bankmachine.py +++ b/milkymist/lasmicon/bankmachine.py @@ -3,6 +3,7 @@ from migen.bus.asmibus import * from migen.genlib.roundrobin import * from migen.genlib.fsm import FSM from migen.genlib.misc import optree +from migen.genlib.fifo import SyncFIFO from milkymist.lasmicon.multiplexer import * @@ -33,19 +34,32 @@ class BankMachine(Module): ### + # Request FIFO + self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size) + self.comb += [ + self.req_fifo.din.we.eq(req.we), + self.req_fifo.din.adr.eq(req.adr), + self.req_fifo.we.eq(req.stb), + req.req_ack.eq(self.req_fifo.writable), + + self.req_fifo.re.eq(req.dat_ack), + req.lock.eq(self.req_fifo.readable) + ] + reqf = self.req_fifo.dout + slicer = _AddressSlicer(geom_settings.col_a, address_align) # Row tracking has_openrow = Signal() openrow = Signal(geom_settings.row_a) hit = Signal() - self.comb += hit.eq(openrow == slicer.row(req.adr)) + self.comb += hit.eq(openrow == slicer.row(reqf.adr)) track_open = Signal() track_close = Signal() self.sync += [ If(track_open, has_openrow.eq(1), - openrow.eq(slicer.row(req.adr)) + openrow.eq(slicer.row(reqf.adr)) ), If(track_close, has_openrow.eq(0) @@ -57,9 +71,9 @@ class BankMachine(Module): self.comb += [ self.cmd.ba.eq(bankn), If(s_row_adr, - self.cmd.a.eq(slicer.row(req.adr)) + self.cmd.a.eq(slicer.row(reqf.adr)) ).Else( - self.cmd.a.eq(slicer.col(req.adr)) + self.cmd.a.eq(slicer.col(reqf.adr)) ) ] @@ -85,16 +99,16 @@ class BankMachine(Module): fsm.act(fsm.REGULAR, If(self.refresh_req, fsm.next_state(fsm.REFRESH) - ).Elif(req.stb, + ).Elif(self.req_fifo.readable, If(has_openrow, If(hit, # NB: write-to-read specification is enforced by multiplexer self.cmd.stb.eq(1), - req.ack.eq(self.cmd.ack), - self.cmd.is_read.eq(~req.we), - self.cmd.is_write.eq(req.we), + req.dat_ack.eq(self.cmd.ack), + self.cmd.is_read.eq(~reqf.we), + self.cmd.is_write.eq(reqf.we), self.cmd.cas_n.eq(0), - self.cmd.we_n.eq(~req.we) + self.cmd.we_n.eq(~reqf.we) ).Else( fsm.next_state(fsm.PRECHARGE) ) diff --git a/top.py b/top.py index 4396b1fd..25fa2ea8 100644 --- a/top.py +++ b/top.py @@ -43,10 +43,10 @@ sdram_timing = lasmicon.TimingSettings( tREFI=ns(7800, False), tRFC=ns(70), - CL=3, read_latency=5, write_latency=0, + req_queue_size=8, read_time=32, write_time=16 ) -- 2.30.2