From e592dd625d5ad569561b081a01ff4a6be24693e0 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Tue, 1 Nov 2016 18:15:57 +0000 Subject: [PATCH] re PR target/78166 (hash.c:1887:1: error: unrecognizable insn) PR target/78166 * config/pa/pa.md: Add new shift/add patterns to handle (plus (mult (reg) (mem_shadd_operand)) (reg)) source operand. From-SVN: r241749 --- gcc/ChangeLog | 6 ++++++ gcc/config/pa/pa.md | 30 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d4fd69bf8f..35d9e722bde 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-01 John David Anglin + + PR target/78166 + * config/pa/pa.md: Add new shift/add patterns to handle + (plus (mult (reg) (mem_shadd_operand)) (reg)) source operand. + 2016-11-01 Max Filippov * config/xtensa/xtensa-protos.h diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index e4c806f84a8..6725504fce9 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -6248,6 +6248,21 @@ [(set_attr "type" "binary") (set_attr "length" "4")]) +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "mem_shadd_operand" "")) + (match_operand:SI 1 "register_operand" "r")))] + "" + "* +{ + int shift_val = exact_log2 (INTVAL (operands[3])); + operands[3] = GEN_INT (shift_val); + return \"{sh%o3addl %2,%1,%0|shladd,l %2,%o3,%1,%0}\"; +}" + [(set_attr "type" "binary") + (set_attr "length" "4")]) + (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (ashift:DI (match_operand:DI 2 "register_operand" "r") @@ -6258,6 +6273,21 @@ [(set_attr "type" "binary") (set_attr "length" "4")]) +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r") + (match_operand:DI 3 "mem_shadd_operand" "")) + (match_operand:DI 1 "register_operand" "r")))] + "TARGET_64BIT" + "* +{ + int shift_val = exact_log2 (INTVAL (operands[3])); + operands[3] = GEN_INT (shift_val); + return \"shladd,l %2,%o3,%1,%0\"; +}" + [(set_attr "type" "binary") + (set_attr "length" "4")]) + (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "") -- 2.30.2