From e5a3263e50faf38a91e248ba1dafe26b6ab0c9ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jul 2019 17:22:57 +0100 Subject: [PATCH] set reset_less=True - the data is protected by muxid. if muxid not set, data is invalid. therefore reset is pointless (and wastes gates) --- src/ieee754/div_rem_sqrt_rsqrt/test_core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py index 3d58d0de..0ee39351 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py @@ -144,10 +144,10 @@ class DivPipeCoreTestPipeline(Elaboratable): for stage_index in range(core_config.num_calculate_stages)] self.final_stage = DivPipeCoreFinalStage(core_config) self.interstage_signals = [ - DivPipeCoreInterstageData(core_config, reset_less=False) + DivPipeCoreInterstageData(core_config, reset_less=True) for i in range(core_config.num_calculate_stages + 1)] - self.i = DivPipeCoreInputData(core_config, reset_less=False) - self.o = DivPipeCoreOutputData(core_config, reset_less=False) + self.i = DivPipeCoreInputData(core_config, reset_less=True) + self.o = DivPipeCoreOutputData(core_config, reset_less=True) def elaborate(self, platform): m = Module() -- 2.30.2