From e61d9eabc6acf093430306a557df286c84a6a12a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Jun 2017 18:08:37 +0200 Subject: [PATCH] board/targets/sim: add identifier --- litex/boards/targets/sim.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 50cac545..1624441f 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -28,6 +28,7 @@ class BaseSoC(SoCSDRAM): SoCSDRAM.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), integrated_rom_size=0x8000, + ident="LiteX simulation example design", with_uart=False, **kwargs) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) -- 2.30.2