From e623c07bce1cd7bec79b96ca9e725bb8c3e8d449 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 24 Aug 2021 12:53:06 +0100 Subject: [PATCH] replace data_o with o_data and data_i with i_data as well a little more care involved here due to names such as st_data_o and others --- src/soc/experiment/alu_fsm.py | 46 +++++------ src/soc/experiment/alu_hier.py | 38 ++++----- src/soc/experiment/compalu.py | 12 +-- src/soc/experiment/compalu_multi.py | 4 +- src/soc/experiment/compldst_multi.py | 12 +-- src/soc/experiment/cscore.py | 6 +- src/soc/experiment/l0_cache.py | 38 ++++----- src/soc/experiment/score6600.py | 50 ++++++------ src/soc/experiment/score6600_multi.py | 50 ++++++------ src/soc/fu/alu/test/test_pipe_caller.py | 8 +- src/soc/fu/branch/test/test_pipe_caller.py | 10 +-- src/soc/fu/compunits/formal/proof_fu.py | 4 +- src/soc/fu/compunits/test/test_compunit.py | 8 +- src/soc/fu/cr/test/test_pipe_caller.py | 8 +- src/soc/fu/div/fsm.py | 16 ++-- src/soc/fu/div/test/helper.py | 8 +- src/soc/fu/logical/test/test_pipe_caller.py | 4 +- src/soc/fu/mmu/fsm.py | 14 ++-- src/soc/fu/mmu/test/test_pipe_caller.py | 8 +- src/soc/fu/mul/test/helper.py | 8 +- src/soc/fu/regspec.py | 6 +- src/soc/fu/shift_rot/test/test_pipe_caller.py | 6 +- src/soc/fu/spr/test/test_pipe_caller.py | 4 +- src/soc/fu/trap/test/test_pipe_caller.py | 4 +- src/soc/regfile/regfile.py | 80 +++++++++---------- src/soc/regfile/virtual_port.py | 56 ++++++------- src/soc/scoreboard/instruction_q.py | 16 ++-- src/soc/scoreboard/test_iq.py | 6 +- src/soc/scoreboard/test_mem2_fu_matrix.py | 10 +-- src/soc/scoreboard/test_mem_fu_matrix.py | 10 +-- src/soc/simple/core.py | 10 +-- src/soc/simple/issuer.py | 42 +++++----- src/soc/simple/test/test_core.py | 2 +- 33 files changed, 302 insertions(+), 302 deletions(-) diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py index 3b0418a3..e2e73773 100644 --- a/src/soc/experiment/alu_fsm.py +++ b/src/soc/experiment/alu_fsm.py @@ -44,8 +44,8 @@ class Shifter(Elaboratable): """Simple sequential shifter Prev port data: - * p.data_i.data: value to be shifted - * p.data_i.shift: shift amount + * p.i_data.data: value to be shifted + * p.i_data.shift: shift amount * When zero, no shift occurs. * On POWER, range is 0 to 63 for 32-bit, * and 0 to 127 for 64-bit. @@ -55,11 +55,11 @@ class Shifter(Elaboratable): * op.sdir: shift direction (0 = left, 1 = right) Next port data: - * n.data_o.data: shifted value + * n.o_data.data: shifted value """ class PrevData: def __init__(self, width): - self.data = Signal(width, name="p_data_i") + self.data = Signal(width, name="p_i_data") self.shift = Signal(width, name="p_shift_i") self.ctx = Dummy() # comply with CompALU API @@ -68,7 +68,7 @@ class Shifter(Elaboratable): class NextData: def __init__(self, width): - self.data = Signal(width, name="n_data_o") + self.data = Signal(width, name="n_o_data") def _get_data(self): return [self.data] @@ -77,14 +77,14 @@ class Shifter(Elaboratable): self.width = width self.p = PrevControl() self.n = NextControl() - self.p.data_i = Shifter.PrevData(width) - self.n.data_o = Shifter.NextData(width) + self.p.i_data = Shifter.PrevData(width) + self.n.o_data = Shifter.NextData(width) # more pieces to make this example class comply with the CompALU API self.op = CompFSMOpSubset(name="op") - self.p.data_i.ctx.op = self.op - self.i = self.p.data_i._get_data() - self.out = self.n.data_o._get_data() + self.p.i_data.ctx.op = self.op + self.i = self.p.i_data._get_data() + self.out = self.n.o_data._get_data() def elaborate(self, platform): m = Module() @@ -115,8 +115,8 @@ class Shifter(Elaboratable): # build the data flow m.d.comb += [ # connect input and output - shift_in.eq(self.p.data_i.data), - self.n.data_o.data.eq(shift_reg), + shift_in.eq(self.p.i_data.data), + self.n.o_data.data.eq(shift_reg), # generate shifted views of the register shift_left_by_1.eq(Cat(0, shift_reg[:-1])), shift_right_by_1.eq(Cat(shift_reg[1:], 0)), @@ -156,7 +156,7 @@ class Shifter(Elaboratable): self.p.o_ready.eq(1), # keep loading the shift register and shift count load.eq(1), - next_count.eq(self.p.data_i.shift), + next_count.eq(self.p.i_data.shift), ] # capture the direction bit as well m.d.sync += direction.eq(self.op.sdir) @@ -188,13 +188,13 @@ class Shifter(Elaboratable): def __iter__(self): yield self.op.sdir - yield self.p.data_i.data - yield self.p.data_i.shift + yield self.p.i_data.data + yield self.p.i_data.shift yield self.p.i_valid yield self.p.o_ready yield self.n.i_ready yield self.n.o_valid - yield self.n.data_o.data + yield self.n.o_data.data def ports(self): return list(self) @@ -222,7 +222,7 @@ def test_shifter(): {'comment': 'Shifter Demonstration'}, ('prev port', [ ('op__sdir', 'in'), - ('p_data_i[7:0]', 'in'), + ('p_i_data[7:0]', 'in'), ('p_shift_i[7:0]', 'in'), ({'submodule': 'p'}, [ ('p_i_valid', 'in'), @@ -232,7 +232,7 @@ def test_shifter(): 'count[3:0]', 'shift_reg[7:0]']), ('next port', [ - ('n_data_o[7:0]', 'out'), + ('n_o_data[7:0]', 'out'), ({'submodule': 'n'}, [ ('n_o_valid', 'out'), ('n_i_ready', 'in')])])] @@ -246,8 +246,8 @@ def test_shifter(): def send(data, shift, direction): # present input data and assert i_valid - yield dut.p.data_i.data.eq(data) - yield dut.p.data_i.shift.eq(shift) + yield dut.p.i_data.data.eq(data) + yield dut.p.i_data.shift.eq(shift) yield dut.op.sdir.eq(direction) yield dut.p.i_valid.eq(1) yield @@ -256,8 +256,8 @@ def test_shifter(): yield # clear input data and negate p.i_valid yield dut.p.i_valid.eq(0) - yield dut.p.data_i.data.eq(0) - yield dut.p.data_i.shift.eq(0) + yield dut.p.i_data.data.eq(0) + yield dut.p.i_data.shift.eq(0) yield dut.op.sdir.eq(0) def receive(expected): @@ -268,7 +268,7 @@ def test_shifter(): while not (yield dut.n.o_valid): yield # read result - result = yield dut.n.data_o.data + result = yield dut.n.o_data.data # negate n.i_ready yield dut.n.i_ready.eq(0) # check result diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 3f92dc75..6541e12c 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -105,10 +105,10 @@ class Dummy: class DummyALU(Elaboratable): def __init__(self, width): self.p = Dummy() # make look like nmutil pipeline API - self.p.data_i = Dummy() - self.p.data_i.ctx = Dummy() + self.p.i_data = Dummy() + self.p.i_data.ctx = Dummy() self.n = Dummy() # make look like nmutil pipeline API - self.n.data_o = Dummy() + self.n.o_data = Dummy() self.p.i_valid = Signal() self.p.o_ready = Signal() self.n.i_ready = Signal() @@ -125,11 +125,11 @@ class DummyALU(Elaboratable): self.o = self.out[0] self.width = width # more "look like nmutil pipeline API" - self.p.data_i.ctx.op = self.op - self.p.data_i.a = self.a - self.p.data_i.b = self.b - self.p.data_i.c = self.c - self.n.data_o.o = self.o + self.p.i_data.ctx.op = self.op + self.p.i_data.a = self.a + self.p.i_data.b = self.b + self.p.i_data.c = self.c + self.n.o_data.o = self.o def elaborate(self, platform): m = Module() @@ -181,10 +181,10 @@ class DummyALU(Elaboratable): class ALU(Elaboratable): def __init__(self, width): self.p = Dummy() # make look like nmutil pipeline API - self.p.data_i = Dummy() - self.p.data_i.ctx = Dummy() + self.p.i_data = Dummy() + self.p.i_data.ctx = Dummy() self.n = Dummy() # make look like nmutil pipeline API - self.n.data_o = Dummy() + self.n.o_data = Dummy() self.p.i_valid = Signal() self.p.o_ready = Signal() self.n.i_ready = Signal() @@ -204,11 +204,11 @@ class ALU(Elaboratable): self.cr = self.out[1] self.width = width # more "look like nmutil pipeline API" - self.p.data_i.ctx.op = self.op - self.p.data_i.a = self.a - self.p.data_i.b = self.b - self.n.data_o.o = self.o - self.n.data_o.cr = self.cr + self.p.i_data.ctx.op = self.op + self.p.i_data.a = self.a + self.p.i_data.b = self.b + self.n.o_data.o = self.o + self.n.o_data.cr = self.cr def elaborate(self, platform): m = Module() @@ -362,10 +362,10 @@ class BranchOp(Elaboratable): class BranchALU(Elaboratable): def __init__(self, width): self.p = Dummy() # make look like nmutil pipeline API - self.p.data_i = Dummy() - self.p.data_i.ctx = Dummy() + self.p.i_data = Dummy() + self.p.i_data.ctx = Dummy() self.n = Dummy() # make look like nmutil pipeline API - self.n.data_o = Dummy() + self.n.o_data = Dummy() self.p.i_valid = Signal() self.p.o_ready = Signal() self.n.i_ready = Signal() diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py index 4d15ff41..ff05b48f 100644 --- a/src/soc/experiment/compalu.py +++ b/src/soc/experiment/compalu.py @@ -61,7 +61,7 @@ class ComputationUnitNoDelay(Elaboratable): self.src2_i = Signal(rwid, reset_less=True) # oper2 in self.busy_o = Signal(reset_less=True) # fn busy out - self.data_o = Signal(rwid, reset_less=True) # Dest out + self.o_data = Signal(rwid, reset_less=True) # Dest out self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request # release request out (o_valid) self.req_rel_o = Signal(reset_less=True) @@ -147,7 +147,7 @@ class ComputationUnitNoDelay(Elaboratable): # output the data from the latch on go_write with m.If(self.go_wr_i): - m.d.comb += self.data_o.eq(data_r) + m.d.comb += self.o_data.eq(data_r) return m @@ -163,7 +163,7 @@ class ComputationUnitNoDelay(Elaboratable): yield self.busy_o yield self.rd_rel_o yield self.req_rel_o - yield self.data_o + yield self.o_data def ports(self): return list(self) @@ -192,18 +192,18 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0): yield yield dut.go_rd_i.eq(0) req_rel_o = yield dut.req_rel_o - result = yield dut.data_o + result = yield dut.o_data print("req_rel", req_rel_o, result) while True: req_rel_o = yield dut.req_rel_o - result = yield dut.data_o + result = yield dut.o_data print("req_rel", req_rel_o, result) if req_rel_o: break yield yield dut.go_wr_i.eq(1) yield - result = yield dut.data_o + result = yield dut.o_data print("result", result) yield dut.go_wr_i.eq(0) yield diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 4d17bad8..536e32bf 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -157,7 +157,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): self.busy_o = cu.busy_o self.dest = cu._dest - self.data_o = self.dest[0] # Dest out + self.o_data = self.dest[0] # Dest out self.done_o = cu.done_o def _mux_op(self, m, sl, op_is_imm, imm, i): @@ -372,7 +372,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): yield self.busy_o yield self.rd.rel_o yield self.wr.rel_o - yield self.data_o + yield self.o_data def ports(self): return list(self) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 975f04f4..d95dfa52 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -141,7 +141,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): Data (outputs) -------------- - * :data_o: Dest out (LD) - managed by wr[0] go/req + * :o_data: Dest out (LD) - managed by wr[0] go/req * :addr_o: Address out (LD or ST) - managed by wr[1] go/req * :exc_o: Address/Data Exception occurred. LD/ST must terminate @@ -236,7 +236,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): self.oper_i = cu.oper_i self.src_i = cu._src_i - self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT + self.o_data = Data(self.data_wid, name="o") # Dest1 out: RT self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA self.exc_o = cu.exc_o self.done_o = cu.done_o @@ -492,7 +492,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): # Data/Address outputs # put the LD-output register directly onto the output bus on a go_write - comb += self.data_o.data.eq(self.dest[0]) + comb += self.o_data.data.eq(self.dest[0]) with m.If(self.wr.go_i[0]): comb += self.dest[0].eq(ldd_r) @@ -563,7 +563,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): to LDSTOutputData o and o1 respectively. """ if i == 0: - return self.data_o # LDSTOutputData.regspec o + return self.o_data # LDSTOutputData.regspec o if i == 1: return self.addr_o # LDSTOutputData.regspec o1 # return self.dest[i] @@ -586,7 +586,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): yield self.adr_rel_o yield self.sto_rel_o yield self.wr.rel_o - yield from self.data_o.ports() + yield from self.o_data.ports() yield from self.addr_o.ports() yield self.load_mem_o yield self.stwd_mem_o @@ -711,7 +711,7 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False, yield from wait_for(dut.wr.rel_o[0], test1st=True) yield dut.wr.go.eq(1) yield - data = yield dut.data_o + data = yield dut.o_data print(data) yield dut.wr.go.eq(0) yield from wait_for(dut.busy_o) diff --git a/src/soc/experiment/cscore.py b/src/soc/experiment/cscore.py index 187918c0..ea6bd320 100644 --- a/src/soc/experiment/cscore.py +++ b/src/soc/experiment/cscore.py @@ -217,7 +217,7 @@ class Scoreboard(Elaboratable): # merge (OR) all integer FU / ALU outputs to a single value # bit of a hack: treereduce needs a list with an item named "dest_o" dest_o = treereduce(int_alus) - m.d.sync += int_dest.data_i.eq(dest_o) + m.d.sync += int_dest.i_data.eq(dest_o) # connect ALUs for i, alu in enumerate(int_alus): @@ -225,8 +225,8 @@ class Scoreboard(Elaboratable): m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i]) m.d.comb += alu.issue_i.eq(fn_issue_l[i]) # m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue - m.d.comb += alu.src1_i.eq(int_src1.data_o) - m.d.comb += alu.src2_i.eq(int_src2.data_o) + m.d.comb += alu.src1_i.eq(int_src1.o_data) + m.d.comb += alu.src2_i.eq(int_src2.o_data) m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready return m diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 8414f77f..f1c895d0 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -126,8 +126,8 @@ class DataMerger(Elaboratable): :addr_array_i: an NxN Array of Signals with bits set indicating address match. bits across the diagonal (addr_array_i[x][x]) will always be set, to indicate "active". - :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit} - :data_o: an Output Record of same type + :i_data: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit} + :o_data: an Output Record of same type {data: 128 bit, byte_enable: 16 bit} """ self.array_size = array_size @@ -141,8 +141,8 @@ class DataMerger(Elaboratable): ul = [] for i in range(array_size): ul.append(DataMergerRecord()) - self.data_i = Array(ul) - self.data_o = DataMergerRecord() + self.i_data = Array(ul) + self.o_data = DataMergerRecord() def elaborate(self, platform): m = Module() @@ -160,10 +160,10 @@ class DataMerger(Elaboratable): select = self.addr_array_i[idx][j] r = DataMergerRecord() with m.If(select): - comb += r.eq(self.data_i[j]) + comb += r.eq(self.i_data[j]) l.append(r) - comb += self.data_o.data.eq(ortreereduce(l, "data")) - comb += self.data_o.en.eq(ortreereduce(l, "en")) + comb += self.o_data.data.eq(ortreereduce(l, "data")) + comb += self.o_data.en.eq(ortreereduce(l, "en")) return m @@ -197,15 +197,15 @@ class TstDataMerger2(Elaboratable): for j in range(self.n_units): inp = self.input_array[j] - m.d.comb += dm_even.data_i[j].en.eq(inp.bytemask_even) - m.d.comb += dm_odd.data_i[j].en.eq(inp.bytemask_odd) - m.d.comb += dm_even.data_i[j].data.eq(inp.data_even) - m.d.comb += dm_odd.data_i[j].data.eq(inp.data_odd) + m.d.comb += dm_even.i_data[j].en.eq(inp.bytemask_even) + m.d.comb += dm_odd.i_data[j].en.eq(inp.bytemask_odd) + m.d.comb += dm_even.i_data[j].data.eq(inp.data_even) + m.d.comb += dm_odd.i_data[j].data.eq(inp.data_odd) m.d.comb += dm_even.addr_array_i[j].eq(self.addr_match(j,addr_even)) m.d.comb += dm_odd.addr_array_i[j].eq(self.addr_match(j,addr_odd)) - m.d.comb += self.data_odd.eq(dm_odd.data_o.data) - m.d.comb += self.data_even.eq(dm_even.data_o.data) + m.d.comb += self.data_odd.eq(dm_odd.o_data.data) + m.d.comb += self.data_even.eq(dm_even.o_data.data) return m @@ -384,20 +384,20 @@ def l0_cache_ldst(arg, dut): def data_merger_merge(dut): # starting with all inputs zero yield Settle() - en = yield dut.data_o.en - data = yield dut.data_o.data + en = yield dut.o_data.en + data = yield dut.o_data.data assert en == 0, "en must be zero" assert data == 0, "data must be zero" yield yield dut.addr_array_i[0].eq(0xFF) for j in range(dut.array_size): - yield dut.data_i[j].en.eq(1 << j) - yield dut.data_i[j].data.eq(0xFF << (16*j)) + yield dut.i_data[j].en.eq(1 << j) + yield dut.i_data[j].data.eq(0xFF << (16*j)) yield Settle() - en = yield dut.data_o.en - data = yield dut.data_o.data + en = yield dut.o_data.en + data = yield dut.o_data.data assert data == 0xff00ff00ff00ff00ff00ff00ff00ff assert en == 0xff yield diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py index 13ecff6b..0104290e 100644 --- a/src/soc/experiment/score6600.py +++ b/src/soc/experiment/score6600.py @@ -107,7 +107,7 @@ class CompUnitsBase(Elaboratable): self.addr_o = Signal(rwid, reset_less=True) # in/out register data (note: not register#, actual data) - self.data_o = Signal(rwid, reset_less=True) + self.o_data = Signal(rwid, reset_less=True) self.src1_i = Signal(rwid, reset_less=True) self.src2_i = Signal(rwid, reset_less=True) # input operand @@ -152,8 +152,8 @@ class CompUnitsBase(Elaboratable): # merge (OR) all integer FU / ALU outputs to a single value if self.units: - data_o = treereduce(self.units, "data_o") - comb += self.data_o.eq(data_o) + o_data = treereduce(self.units, "o_data") + comb += self.o_data.eq(o_data) if self.ldstmode: addr_o = treereduce(self.units, "addr_o") comb += self.addr_o.eq(addr_o) @@ -679,11 +679,11 @@ class Scoreboard(Elaboratable): # branch is active (TODO: a better signal: this is over-using the # go_write signal - actually the branch should not be "writing") with m.If(br1.go_wr_i): - sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2)) + sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2)) sync += bspec.active_i.eq(0) comb += bspec.br_i.eq(1) # branch occurs if data == 1, failed if data == 0 - comb += bspec.br_ok_i.eq(br1.data_o == 1) + comb += bspec.br_ok_i.eq(br1.o_data == 1) for i in range(n_intfus): # *expected* direction of the branch matched against *actual* comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i]) @@ -698,9 +698,9 @@ class Scoreboard(Elaboratable): comb += int_src2.ren.eq(intfus.src2_rsel_o) # connect ALUs to regfile - comb += int_dest.data_i.eq(cu.data_o) - comb += cu.src1_i.eq(int_src1.data_o) - comb += cu.src2_i.eq(int_src2.data_o) + comb += int_dest.i_data.eq(cu.o_data) + comb += cu.src1_i.eq(int_src1.o_data) + comb += cu.src2_i.eq(int_src2.o_data) # connect ALU Computation Units comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) @@ -735,9 +735,9 @@ class IssueToScoreboard(Elaboratable): self.n_regs = n_regs mqbits = unsigned(int(log(qlen) / log(2))+2) - self.p_add_i = Signal(mqbits) # instructions to add (from data_i) + self.p_add_i = Signal(mqbits) # instructions to add (from i_data) self.p_o_ready = Signal() # instructions were added - self.data_i = Instruction._nq(n_in, "data_i") + self.i_data = Instruction._nq(n_in, "i_data") self.busy_o = Signal(reset_less=True) # at least one CU is busy self.qlen_o = Signal(mqbits, reset_less=True) @@ -764,7 +764,7 @@ class IssueToScoreboard(Elaboratable): comb += iq.p_add_i.eq(self.p_add_i) comb += self.p_o_ready.eq(iq.p_o_ready) for i in range(self.n_in): - comb += eq(iq.data_i[i], self.data_i[i]) + comb += eq(iq.i_data[i], self.i_data[i]) # take instruction and process it. note that it's possible to # "inspect" the queue contents *without* actually removing the @@ -793,7 +793,7 @@ class IssueToScoreboard(Elaboratable): # "resetting" done above (insn_i=0) could be re-ASSERTed. with m.If(iq.qlen_o != 0): # get the operands and operation - instr = iq.data_o[0] + instr = iq.o_data[0] imm = instr.imm_data.data dest = instr.write_reg.data src1 = instr.read_reg1.data @@ -840,7 +840,7 @@ class IssueToScoreboard(Elaboratable): def __iter__(self): yield self.p_o_ready - for o in self.data_i: + for o in self.i_data: yield from list(o) yield self.p_add_i @@ -853,7 +853,7 @@ def power_instr_q(dut, pdecode2, ins, code): sendlen = 1 for idx, instr in enumerate(instrs): - yield dut.data_i[idx].eq(instr) + yield dut.i_data[idx].eq(instr) insn_type = yield instr.insn_type fn_unit = yield instr.fn_unit print("senddata ", idx, insn_type, fn_unit, instr) @@ -881,17 +881,17 @@ def instr_q(dut, op, funit, op_imm, imm, src1, src2, dest, dest = instr['write_reg'] insn_type = instr['insn_type'] fn_unit = instr['fn_unit'] - yield dut.data_i[idx].insn_type.eq(insn_type) - yield dut.data_i[idx].fn_unit.eq(fn_unit) - yield dut.data_i[idx].read_reg1.data.eq(reg1) - yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO - yield dut.data_i[idx].read_reg2.data.eq(reg2) - yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO - yield dut.data_i[idx].write_reg.data.eq(dest) - yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO - yield dut.data_i[idx].imm_data.data.eq(imm) - yield dut.data_i[idx].imm_data.ok.eq(op_imm) - di = yield dut.data_i[idx] + yield dut.i_data[idx].insn_type.eq(insn_type) + yield dut.i_data[idx].fn_unit.eq(fn_unit) + yield dut.i_data[idx].read_reg1.data.eq(reg1) + yield dut.i_data[idx].read_reg1.ok.eq(1) # XXX TODO + yield dut.i_data[idx].read_reg2.data.eq(reg2) + yield dut.i_data[idx].read_reg2.ok.eq(1) # XXX TODO + yield dut.i_data[idx].write_reg.data.eq(dest) + yield dut.i_data[idx].write_reg.ok.eq(1) # XXX TODO + yield dut.i_data[idx].imm_data.data.eq(imm) + yield dut.i_data[idx].imm_data.ok.eq(op_imm) + di = yield dut.i_data[idx] print("senddata %d %x" % (idx, di)) yield dut.p_add_i.eq(sendlen) yield diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index ff35b676..e2498ef5 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -115,7 +115,7 @@ class CompUnitsBase(Elaboratable): self.addr_o = Signal(rwid, reset_less=True) # in/out register data (note: not register#, actual data) - self.data_o = Signal(rwid, reset_less=True) + self.o_data = Signal(rwid, reset_less=True) self.src1_i = Signal(rwid, reset_less=True) self.src2_i = Signal(rwid, reset_less=True) # input operand @@ -170,8 +170,8 @@ class CompUnitsBase(Elaboratable): # protected by a single go_wr. multi-issue requires a bus # to be inserted here. if self.units: - data_o = ortreereduce(self.units, "data_o") - comb += self.data_o.eq(data_o) + o_data = ortreereduce(self.units, "o_data") + comb += self.o_data.eq(o_data) if self.ldstmode: addr_o = ortreereduce(self.units, "addr_o") comb += self.addr_o.eq(addr_o) @@ -730,11 +730,11 @@ class Scoreboard(Elaboratable): # branch is active (TODO: a better signal: this is over-using the # go_write signal - actually the branch should not be "writing") with m.If(br1.go_wr_i): - sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2)) + sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2)) sync += bspec.active_i.eq(0) comb += bspec.br_i.eq(1) # branch occurs if data == 1, failed if data == 0 - comb += bspec.br_ok_i.eq(br1.data_o == 1) + comb += bspec.br_ok_i.eq(br1.o_data == 1) for i in range(n_intfus): # *expected* direction of the branch matched against *actual* comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i]) @@ -749,9 +749,9 @@ class Scoreboard(Elaboratable): comb += int_src2.ren.eq(intfus.src_rsel_o[1]) # connect ALUs to regfile - comb += int_dest.data_i.eq(cu.data_o) - comb += cu.src1_i.eq(int_src1.data_o) - comb += cu.src2_i.eq(int_src2.data_o) + comb += int_dest.i_data.eq(cu.o_data) + comb += cu.src1_i.eq(int_src1.o_data) + comb += cu.src2_i.eq(int_src2.o_data) # connect ALU Computation Units for i in range(fu_n_src): @@ -788,9 +788,9 @@ class IssueToScoreboard(Elaboratable): self.n_regs = n_regs mqbits = unsigned(int(log(qlen) / log(2))+2) - self.p_add_i = Signal(mqbits) # instructions to add (from data_i) + self.p_add_i = Signal(mqbits) # instructions to add (from i_data) self.p_o_ready = Signal() # instructions were added - self.data_i = Instruction._nq(n_in, "data_i") + self.i_data = Instruction._nq(n_in, "i_data") self.busy_o = Signal(reset_less=True) # at least one CU is busy self.qlen_o = Signal(mqbits, reset_less=True) @@ -817,7 +817,7 @@ class IssueToScoreboard(Elaboratable): comb += iq.p_add_i.eq(self.p_add_i) comb += self.p_o_ready.eq(iq.p_o_ready) for i in range(self.n_in): - comb += eq(iq.data_i[i], self.data_i[i]) + comb += eq(iq.i_data[i], self.i_data[i]) # take instruction and process it. note that it's possible to # "inspect" the queue contents *without* actually removing the @@ -846,7 +846,7 @@ class IssueToScoreboard(Elaboratable): # "resetting" done above (insn_i=0) could be re-ASSERTed. with m.If(iq.qlen_o != 0): # get the operands and operation - instr = iq.data_o[0] + instr = iq.o_data[0] imm = instr.imm_data.data dest = instr.write_reg.data src1 = instr.read_reg1.data @@ -886,7 +886,7 @@ class IssueToScoreboard(Elaboratable): def __iter__(self): yield self.p_o_ready - for o in self.data_i: + for o in self.i_data: yield from list(o) yield self.p_add_i @@ -899,7 +899,7 @@ def power_instr_q(dut, pdecode2, ins, code): sendlen = 1 for idx, instr in enumerate(instrs): - yield dut.data_i[idx].eq(instr) + yield dut.i_data[idx].eq(instr) insn_type = yield instr.insn_type fn_unit = yield instr.fn_unit print("senddata ", idx, insn_type, fn_unit, instr) @@ -927,17 +927,17 @@ def instr_q(dut, op, funit, op_imm, imm, src1, src2, dest, dest = instr['write_reg'] insn_type = instr['insn_type'] fn_unit = instr['fn_unit'] - yield dut.data_i[idx].insn_type.eq(insn_type) - yield dut.data_i[idx].fn_unit.eq(fn_unit) - yield dut.data_i[idx].read_reg1.data.eq(reg1) - yield dut.data_i[idx].read_reg1.ok.eq(1) # XXX TODO - yield dut.data_i[idx].read_reg2.data.eq(reg2) - yield dut.data_i[idx].read_reg2.ok.eq(1) # XXX TODO - yield dut.data_i[idx].write_reg.data.eq(dest) - yield dut.data_i[idx].write_reg.ok.eq(1) # XXX TODO - yield dut.data_i[idx].imm_data.data.eq(imm) - yield dut.data_i[idx].imm_data.ok.eq(op_imm) - di = yield dut.data_i[idx] + yield dut.i_data[idx].insn_type.eq(insn_type) + yield dut.i_data[idx].fn_unit.eq(fn_unit) + yield dut.i_data[idx].read_reg1.data.eq(reg1) + yield dut.i_data[idx].read_reg1.ok.eq(1) # XXX TODO + yield dut.i_data[idx].read_reg2.data.eq(reg2) + yield dut.i_data[idx].read_reg2.ok.eq(1) # XXX TODO + yield dut.i_data[idx].write_reg.data.eq(dest) + yield dut.i_data[idx].write_reg.ok.eq(1) # XXX TODO + yield dut.i_data[idx].imm_data.data.eq(imm) + yield dut.i_data[idx].imm_data.ok.eq(op_imm) + di = yield dut.i_data[idx] print("senddata %d %x" % (idx, di)) yield dut.p_add_i.eq(sendlen) yield diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 422a9a61..facb8df9 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -38,7 +38,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) @@ -126,7 +126,7 @@ class TestRunner(unittest.TestCase): pspec = ALUPipeSpec(id_wid=2) m.submodules.alu = alu = ALUBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -158,8 +158,8 @@ class TestRunner(unittest.TestCase): oe_ok = yield dec2.e.do.oe.ok if not oe or not oe_ok: # if OE not enabled, XER SO and OV must correspondingly be false - so_ok = yield alu.n.data_o.xer_so.ok - ov_ok = yield alu.n.data_o.xer_ov.ok + so_ok = yield alu.n.o_data.xer_so.ok + ov_ok = yield alu.n.o_data.xer_ov.ok self.assertEqual(so_ok, False, code) self.assertEqual(ov_ok, False, code) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index d144f407..0c5b3b95 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -73,7 +73,7 @@ class TestRunner(unittest.TestCase): pspec = BranchPipeSpec(id_wid=2) m.submodules.branch = branch = BranchBasePipe(pspec) - comb += branch.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += branch.p.valid_i.eq(1) comb += branch.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) @@ -141,11 +141,11 @@ class TestRunner(unittest.TestCase): sim.run() def assert_outputs(self, branch, dec2, sim, prev_nia, code): - branch_taken = yield branch.n.data_o.nia.ok + branch_taken = yield branch.n.o_data.nia.ok sim_branch_taken = prev_nia != sim.pc.CIA self.assertEqual(branch_taken, sim_branch_taken, code) if branch_taken: - branch_addr = yield branch.n.data_o.nia.data + branch_addr = yield branch.n.o_data.nia.data print(f"real: {branch_addr:x}, sim: {sim.pc.CIA.value:x}") self.assertEqual(branch_addr, sim.pc.CIA.value, code) @@ -153,10 +153,10 @@ class TestRunner(unittest.TestCase): # TODO: this should be checking write_fast2 lk = yield dec2.e.do.lk - branch_lk = yield branch.n.data_o.lr.ok + branch_lk = yield branch.n.o_data.lr.ok self.assertEqual(lk, branch_lk, code) if lk: - branch_lr = yield branch.n.data_o.lr.data + branch_lr = yield branch.n.o_data.lr.data self.assertEqual(sim.spr['LR'], branch_lr, code) def set_inputs(self, branch, dec2, sim): diff --git a/src/soc/fu/compunits/formal/proof_fu.py b/src/soc/fu/compunits/formal/proof_fu.py index e8a5e50f..06437df0 100644 --- a/src/soc/fu/compunits/formal/proof_fu.py +++ b/src/soc/fu/compunits/formal/proof_fu.py @@ -149,8 +149,8 @@ class Driver(Elaboratable): # then the alu data should be output with m.If(Past(wr_rel) & Past(go_wr)): # the alu data is output - comb += Assert((dut.data_o == alu_temp) - | (dut.data_o == dut.alu.o)) + comb += Assert((dut.o_data == alu_temp) + | (dut.o_data == dut.alu.o)) # wr_rel is dropped comb += Assert(wr_rel == 0) # busy is dropped. diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 2ce9f2d0..5ed526ec 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -226,9 +226,9 @@ class TestRunner(FHDLTestCase): fast_out2 = yield pdecode2.e.write_fast2.data fast_out2_ok = yield pdecode2.e.write_fast2.ok print("lk:", lk, fast_out2, fast_out2_ok) - op_lk = yield cu.alu.pipe1.p.data_i.ctx.op.lk + op_lk = yield cu.alu.pipe1.p.i_data.ctx.op.lk print("op_lk:", op_lk) - print(dir(cu.alu.pipe1.n.data_o)) + print(dir(cu.alu.pipe1.n.o_data)) fn_unit = yield pdecode2.e.do.fn_unit fuval = self.funit.value self.assertEqual(fn_unit & fuval, fuval) @@ -298,8 +298,8 @@ class TestRunner(FHDLTestCase): # debugging issue with branch if self.funit == Function.BRANCH: - lr = yield cu.alu.pipe1.n.data_o.lr.data - lr_ok = yield cu.alu.pipe1.n.data_o.lr.ok + lr = yield cu.alu.pipe1.n.o_data.lr.data + lr_ok = yield cu.alu.pipe1.n.o_data.lr.ok print("lr:", hex(lr), lr_ok) if self.funit == Function.LDST: diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index 63526980..0c2af709 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -76,7 +76,7 @@ class TestRunner(unittest.TestCase): cr_en = yield dec2.e.write_cr.ok if whole_reg_ok: - full_cr = yield alu.n.data_o.full_cr.data & full_cr_mask + full_cr = yield alu.n.o_data.full_cr.data & full_cr_mask expected_cr = simulator.cr.value print("CR whole: expected %x, actual: %x mask: %x" % \ (expected_cr, full_cr, full_cr_mask)) @@ -87,10 +87,10 @@ class TestRunner(unittest.TestCase): expected_cr = simulator.cr.value print(f"CR whole: {expected_cr:x}, sel {cr_sel}") expected_cr = simulator.crl[cr_sel].get_range().value - real_cr = yield alu.n.data_o.cr.data + real_cr = yield alu.n.o_data.cr.data print(f"CR part: expected {expected_cr:x}, actual: {real_cr:x}") self.assertEqual(expected_cr, real_cr, code) - alu_out = yield alu.n.data_o.o.data + alu_out = yield alu.n.o_data.o.data out_reg_valid = yield dec2.e.write_reg.ok if out_reg_valid: write_reg_idx = yield dec2.e.write_reg.data @@ -147,7 +147,7 @@ class TestRunner(unittest.TestCase): pspec = CRPipeSpec(id_wid=2) m.submodules.alu = alu = CRBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/div/fsm.py b/src/soc/fu/div/fsm.py index afb11174..1b22ca6f 100644 --- a/src/soc/fu/div/fsm.py +++ b/src/soc/fu/div/fsm.py @@ -134,8 +134,8 @@ class FSMDivCoreStage(ControlBase): def __init__(self, pspec): super().__init__() self.pspec = pspec - self.p.data_i = CoreInputData(pspec) - self.n.data_o = CoreOutputData(pspec) + self.p.i_data = CoreInputData(pspec) + self.n.o_data = CoreOutputData(pspec) self.saved_input_data = CoreInputData(pspec) self.empty = Signal(reset=1) self.saved_state = DivState(64, name="saved_state") @@ -147,10 +147,10 @@ class FSMDivCoreStage(ControlBase): m = super().elaborate(platform) m.submodules.div_state_next = self.div_state_next m.submodules.div_state_init = self.div_state_init - data_i = self.p.data_i - data_o = self.n.data_o - core_i = data_i.core - core_o = data_o.core + i_data = self.p.i_data + o_data = self.n.o_data + core_i = i_data.core + core_o = o_data.core core_saved_i = self.saved_input_data.core @@ -158,7 +158,7 @@ class FSMDivCoreStage(ControlBase): m.d.comb += self.div_state_init.dividend.eq(core_i.dividend) - m.d.comb += data_o.eq_without_core(self.saved_input_data) + m.d.comb += o_data.eq_without_core(self.saved_input_data) m.d.comb += core_o.quotient_root.eq(self.div_state_next.o.quotient) # fract width of `DivPipeCoreOutputData.remainder` remainder_fract_width = 64 * 3 @@ -177,7 +177,7 @@ class FSMDivCoreStage(ControlBase): m.d.comb += self.div_state_next.divisor.eq(core_i.divisor_radicand) with m.If(self.p.i_valid): m.d.sync += self.empty.eq(0) - m.d.sync += self.saved_input_data.eq(data_i) + m.d.sync += self.saved_input_data.eq(i_data) with m.Else(): m.d.comb += [ self.div_state_next.i.eq(self.saved_state), diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 15f9d826..98d2b9ed 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -41,7 +41,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) @@ -166,7 +166,7 @@ class DivTestHelper(unittest.TestCase): pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind) m.submodules.alu = alu = DivBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -232,8 +232,8 @@ class DivTestHelper(unittest.TestCase): print("oe, oe_ok", oe, oe_ok) if not oe or not oe_ok: # if OE not enabled, XER SO and OV must not be activated - so_ok = yield alu.n.data_o.xer_so.ok - ov_ok = yield alu.n.data_o.xer_ov.ok + so_ok = yield alu.n.o_data.xer_so.ok + ov_ok = yield alu.n.o_data.xer_ov.ok print("so, ov", so_ok, ov_ok) self.assertEqual(ov_ok, False, code) self.assertEqual(so_ok, False, code) diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index ca14b271..293682e3 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -39,7 +39,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) print ("set alu inputs", inp) @@ -119,7 +119,7 @@ class TestRunner(FHDLTestCase): pspec = LogicalPipeSpec(id_wid=2) m.submodules.alu = alu = LogicalBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 272c4638..800c7f2a 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -42,8 +42,8 @@ class FSMMMUStage(ControlBase): self.pspec = pspec # set up p/n data - self.p.data_i = MMUInputData(pspec) - self.n.data_o = MMUOutputData(pspec) + self.p.i_data = MMUInputData(pspec) + self.n.o_data = MMUOutputData(pspec) self.mmu = MMU() @@ -52,7 +52,7 @@ class FSMMMUStage(ControlBase): self.illegal = Signal() # for SPR field number access - i = self.p.data_i + i = self.p.i_data self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn]) self.fields.create_specs() @@ -86,11 +86,11 @@ class FSMMMUStage(ControlBase): comb += l_in.eq(ldst.m_out) comb += ldst.m_in.eq(l_out) - data_i, data_o = self.p.data_i, self.n.data_o - a_i, b_i, o, spr1_o = data_i.ra, data_i.rb, data_o.o, data_o.spr1 - op = data_i.ctx.op + i_data, o_data = self.p.i_data, self.n.o_data + a_i, b_i, o, spr1_o = i_data.ra, i_data.rb, o_data.o, o_data.spr1 + op = i_data.ctx.op msr_i = op.msr - spr1_i = data_i.spr1 + spr1_i = i_data.spr1 # these are set / got here *ON BEHALF* of LoadStore1 dsisr, dar = ldst.dsisr, ldst.dar diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index a8fcfac5..10c4b048 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -34,7 +34,7 @@ debughang = 1 def set_fsm_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b print("Error here") inp = yield from get_cu_inputs(dec2, sim) @@ -134,8 +134,8 @@ class TestRunner(unittest.TestCase): #print("oe, oe_ok", oe, oe_ok) #if not oe or not oe_ok: # # if OE not enabled, XER SO and OV must not be activated - # so_ok = yield alu.n.data_o.xer_so.ok - # ov_ok = yield alu.n.data_o.xer_ov.ok + # so_ok = yield alu.n.o_data.xer_so.ok + # ov_ok = yield alu.n.o_data.xer_ov.ok # print("so, ov", so_ok, ov_ok) # self.assertEqual(ov_ok, False, code) # self.assertEqual(so_ok, False, code) @@ -224,7 +224,7 @@ class TestRunner(unittest.TestCase): #FIXME connect fsm inputs - comb += fsm.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += fsm.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += fsm.p.valid_i.eq(1) comb += fsm.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py index 06f1a56f..7266223a 100644 --- a/src/soc/fu/mul/test/helper.py +++ b/src/soc/fu/mul/test/helper.py @@ -42,7 +42,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim, has_third_input): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) print("set alu inputs", inp) @@ -151,7 +151,7 @@ class MulTestHelper(unittest.TestCase): pspec = MulPipeSpec(id_wid=2) m.submodules.alu = alu = MulBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -183,8 +183,8 @@ class MulTestHelper(unittest.TestCase): oe_ok = yield dec2.e.do.oe.ok if not oe or not oe_ok: # if OE not enabled, XER SO and OV must correspondingly be false - so_ok = yield alu.n.data_o.xer_so.ok - ov_ok = yield alu.n.data_o.xer_ov.ok + so_ok = yield alu.n.o_data.xer_so.ok + ov_ok = yield alu.n.o_data.xer_ov.ok self.assertEqual(so_ok, False, code) self.assertEqual(ov_ok, False, code) diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py index 07d07120..f6d90d9e 100644 --- a/src/soc/fu/regspec.py +++ b/src/soc/fu/regspec.py @@ -92,15 +92,15 @@ class RegSpecALUAPI(RegSpecAPI): if isinstance(self.rwid, int): # old - testing - API (rwid is int) return self.alu.out[i] # regspec-based API: look up variable through regspec thru row number - return getattr(self.alu.n.data_o, self.get_out_name(i)) + return getattr(self.alu.n.o_data, self.get_out_name(i)) def get_in(self, i): if isinstance(self.rwid, int): # old - testing - API (rwid is int) return self.alu.i[i] # regspec-based API: look up variable through regspec thru row number - return getattr(self.alu.p.data_i, self.get_in_name(i)) + return getattr(self.alu.p.i_data, self.get_in_name(i)) def get_op(self): if isinstance(self.rwid, int): # old - testing - API (rwid is int) return self.alu.op - return self.alu.p.data_i.ctx.op + return self.alu.p.i_data.ctx.op diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index ce1b8401..ac7a4092 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -38,7 +38,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) @@ -119,7 +119,7 @@ class TestRunner(unittest.TestCase): yield vld = yield alu.n.valid_o yield - alu_out = yield alu.n.data_o.o.data + alu_out = yield alu.n.o_data.o.data yield from self.check_alu_outputs(alu, pdecode2, simulator, code) @@ -139,7 +139,7 @@ class TestRunner(unittest.TestCase): pspec = ShiftRotPipeSpec(id_wid=2) m.submodules.alu = alu = ShiftRotBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index 8dc13da5..fbe2314d 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -46,7 +46,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) @@ -142,7 +142,7 @@ class TestRunner(unittest.TestCase): pspec = SPRPipeSpec(id_wid=2) m.submodules.alu = alu = SPRBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.p.valid_i.eq(1) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 26b12ff6..71ed8277 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -49,7 +49,7 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) @@ -90,7 +90,7 @@ class TestRunner(unittest.TestCase): pspec = TrapPipeSpec(id_wid=2) m.submodules.alu = alu = TrapBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) comb += alu.p.valid_i.eq(1) comb += alu.n.ready_i.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index 710fc268..c3f33393 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -42,14 +42,14 @@ class Register(Elaboratable): def read_port(self, name=None): port = RecordObject([("ren", 1), - ("data_o", self.width)], + ("o_data", self.width)], name=name) self._rdports.append(port) return port def write_port(self, name=None): port = RecordObject([("wen", 1), - ("data_i", self.width)], + ("i_data", self.width)], name=name) self._wrports.append(port) return port @@ -65,24 +65,24 @@ class Register(Elaboratable): # read ports. has write-through detection (returns data written) for rp in self._rdports: - domain += rp.data_o.eq(0) + domain += rp.o_data.eq(0) with m.If(rp.ren): if self.writethru: wr_detect = Signal(reset_less=False) m.d.comb += wr_detect.eq(0) for wp in self._wrports: with m.If(wp.wen): - domain += rp.data_o.eq(wp.data_i) + domain += rp.o_data.eq(wp.i_data) m.d.comb += wr_detect.eq(1) with m.If(~wr_detect): - domain += rp.data_o.eq(reg) + domain += rp.o_data.eq(reg) else: - domain += rp.data_o.eq(reg) + domain += rp.o_data.eq(reg) # write ports, delayed by 1 cycle for wp in self._wrports: with m.If(wp.wen): - m.d.sync += reg.eq(wp.data_i) + m.d.sync += reg.eq(wp.i_data) return m @@ -96,7 +96,7 @@ class Register(Elaboratable): res = list(self) -def ortreereduce(tree, attr="data_o"): +def ortreereduce(tree, attr="o_data"): return treereduce(tree, operator.or_, lambda x: getattr(x, attr)) @@ -135,7 +135,7 @@ class RegFileArray(Elaboratable): regs = self.read_reg_port(name) regs = Array(regs) port = RecordObject([("ren", self.depth), - ("data_o", self.width)], name) + ("o_data", self.width)], name) self._rdports.append((regs, port)) return port @@ -143,7 +143,7 @@ class RegFileArray(Elaboratable): regs = self.write_reg_port(name) regs = Array(regs) port = RecordObject([("wen", self.depth), - ("data_i", self.width)]) + ("i_data", self.width)]) self._wrports.append((regs, port)) return port @@ -171,13 +171,13 @@ class RegFileArray(Elaboratable): ren_delay = Signal.like(p.ren) m.d.sync += ren_delay.eq(p.ren) with m.If(ren_delay): - m.d.comb += p.data_o.eq(ror) + m.d.comb += p.o_data.eq(ror) else: - m.d.comb += p.data_o.eq(ror) + m.d.comb += p.o_data.eq(ror) for (regs, p) in self._wrports: m.d.comb += self._get_en_sig(regs, 'wen').eq(p.wen) for r in regs: - m.d.comb += r.data_i.eq(p.data_i) + m.d.comb += r.i_data.eq(p.i_data) return m @@ -203,7 +203,7 @@ class RegFileMem(Elaboratable): bsz = log2_int(self.depth, False) port = RecordObject([("addr", bsz), ("ren", 1), - ("data_o", self.width)], name=name) + ("o_data", self.width)], name=name) if self.synced: domain = "sync" else: @@ -215,7 +215,7 @@ class RegFileMem(Elaboratable): bsz = log2_int(self.depth, False) port = RecordObject([("addr", bsz), ("wen", 1), - ("data_i", self.width)], name=name) + ("i_data", self.width)], name=name) self._wrports[name] = (port, self.memory.write_port()) return port @@ -235,25 +235,25 @@ class RegFileMem(Elaboratable): addrmatch = Signal(reset_less=False) m.d.comb += addrmatch.eq(wp.addr == rp.addr) with m.If(wp.wen & addrmatch): - m.d.comb += rp.data_o.eq(wp.data_i) + m.d.comb += rp.o_data.eq(wp.i_data) m.d.comb += wr_detect.eq(1) with m.If(~wr_detect): - m.d.comb += rp.data_o.eq(rport.data) + m.d.comb += rp.o_data.eq(rport.data) else: if self.synced: ren_delay = Signal.like(rp.ren) m.d.sync += ren_delay.eq(rp.ren) with m.If(ren_delay): - m.d.comb += rp.data_o.eq(rport.data) + m.d.comb += rp.o_data.eq(rport.data) else: - m.d.comb += rp.data_o.eq(rport.data) + m.d.comb += rp.o_data.eq(rport.data) # write ports, delayed by one cycle (in the memory itself) for name, (port, wp) in self._wrports.items(): setattr(m.submodules, "wp_"+name, wp) comb += wp.addr.eq(port.addr) comb += wp.en.eq(port.wen) - comb += wp.data.eq(port.data_i) + comb += wp.data.eq(port.i_data) return m @@ -270,7 +270,7 @@ class RegFile(Elaboratable): bsz = int(log(self.width) / log(2)) port = RecordObject([("addr", bsz), ("ren", 1), - ("data_o", self.width)], name=name) + ("o_data", self.width)], name=name) self._rdports.append(port) return port @@ -278,7 +278,7 @@ class RegFile(Elaboratable): bsz = int(log(self.width) / log(2)) port = RecordObject([("addr", bsz), ("wen", 1), - ("data_i", self.width)], name=name) + ("i_data", self.width)], name=name) self._wrports.append(port) return port @@ -296,15 +296,15 @@ class RegFile(Elaboratable): addrmatch = Signal(reset_less=False) m.d.comb += addrmatch.eq(wp.addr == rp.addr) with m.If(wp.wen & addrmatch): - m.d.comb += rp.data_o.eq(wp.data_i) + m.d.comb += rp.o_data.eq(wp.i_data) m.d.comb += wr_detect.eq(1) with m.If(~wr_detect): - m.d.comb += rp.data_o.eq(regs[rp.addr]) + m.d.comb += rp.o_data.eq(regs[rp.addr]) # write ports, delayed by one cycle for wp in self._wrports: with m.If(wp.wen): - m.d.sync += regs[wp.addr].eq(wp.data_i) + m.d.sync += regs[wp.addr].eq(wp.i_data) return m @@ -323,7 +323,7 @@ class RegFile(Elaboratable): def regfile_sim(dut, rp, wp): yield wp.addr.eq(1) - yield wp.data_i.eq(2) + yield wp.i_data.eq(2) yield wp.wen.eq(1) yield yield wp.wen.eq(0) @@ -333,13 +333,13 @@ def regfile_sim(dut, rp, wp): yield rp.ren.eq(1) yield rp.addr.eq(1) yield Settle() - data = yield rp.data_o + data = yield rp.o_data print(data) yield - data = yield rp.data_o + data = yield rp.o_data print(data) yield - data2 = yield rp.data_o + data2 = yield rp.o_data print(data2) assert data == 2 yield @@ -348,32 +348,32 @@ def regfile_sim(dut, rp, wp): yield rp.addr.eq(5) yield rp.ren.eq(1) yield wp.wen.eq(1) - yield wp.data_i.eq(6) + yield wp.i_data.eq(6) yield - data = yield rp.data_o + data = yield rp.o_data print(data) assert data == 6 yield yield wp.wen.eq(0) yield rp.ren.eq(0) yield - data = yield rp.data_o + data = yield rp.o_data print(data) assert data == 0 yield - data = yield rp.data_o + data = yield rp.o_data print(data) def regfile_array_sim(dut, rp1, rp2, wp, wp2): print("regfile_array_sim") - yield wp.data_i.eq(2) + yield wp.i_data.eq(2) yield wp.wen.eq(1 << 1) yield yield wp.wen.eq(0) yield rp1.ren.eq(1 << 1) yield Settle() - data = yield rp1.data_o + data = yield rp1.o_data print(data) assert data == 2 yield @@ -381,9 +381,9 @@ def regfile_array_sim(dut, rp1, rp2, wp, wp2): yield rp1.ren.eq(1 << 5) yield rp2.ren.eq(1 << 1) yield wp.wen.eq(1 << 5) - yield wp.data_i.eq(6) + yield wp.i_data.eq(6) yield Settle() - data = yield rp1.data_o + data = yield rp1.o_data assert data == 6 print(data) yield @@ -391,15 +391,15 @@ def regfile_array_sim(dut, rp1, rp2, wp, wp2): yield rp1.ren.eq(0) yield rp2.ren.eq(0) yield Settle() - data1 = yield rp1.data_o + data1 = yield rp1.o_data print(data1) assert data1 == 0 - data2 = yield rp2.data_o + data2 = yield rp2.o_data print(data2) assert data2 == 0 yield - data = yield rp1.data_o + data = yield rp1.o_data print(data) assert data == 0 diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py index f4393e15..9bb67028 100644 --- a/src/soc/regfile/virtual_port.py +++ b/src/soc/regfile/virtual_port.py @@ -27,15 +27,15 @@ class VirtualRegPort(RegFileArray): # "full" depth variant of the "external" port self.full_wr = RecordObject([("wen", n_regs), - ("data_i", bitwidth)], # *full* wid + ("i_data", bitwidth)], # *full* wid name="full_wr") self.full_rd = RecordObject([("ren", n_regs), - ("data_o", bitwidth)], # *full* wid + ("o_data", bitwidth)], # *full* wid name="full_rd") if not rd2: return self.full_rd2 = RecordObject([("ren", n_regs), - ("data_o", bitwidth)], # *full* wid + ("o_data", bitwidth)], # *full* wid name="full_rd2") def connect_full_rd(self, m, rfull, name): @@ -43,10 +43,10 @@ class VirtualRegPort(RegFileArray): rd_regs = self.read_reg_port(name) # wire up the enable signals and chain-accumulate the data - l = map(lambda port: port.data_o, rd_regs) # get port data(s) + l = map(lambda port: port.o_data, rd_regs) # get port data(s) le = map(lambda port: port.ren, rd_regs) # get port ren(s) - comb += rfull.data_o.eq(Cat(*l)) # we like Cat on lists + comb += rfull.o_data.eq(Cat(*l)) # we like Cat on lists comb += Cat(*le).eq(rfull.ren) def elaborate(self, platform): @@ -65,11 +65,11 @@ class VirtualRegPort(RegFileArray): wfull = self.full_wr # wire up the enable signals from the large (full) port - l = map(lambda port: port.data_i, wr_regs) + l = map(lambda port: port.i_data, wr_regs) le = map(lambda port: port.wen, wr_regs) # get port wen(s) - # get list of all data_i (and wens) and assign to them via Cat - comb += Cat(*l).eq(wfull.data_i) + # get list of all i_data (and wens) and assign to them via Cat + comb += Cat(*l).eq(wfull.i_data) comb += Cat(*le).eq(wfull.wen) return m @@ -82,14 +82,14 @@ class VirtualRegPort(RegFileArray): def regfile_array_sim(dut, rp1, rp2, rp3, wp): # part-port write - yield wp.data_i.eq(2) + yield wp.i_data.eq(2) yield wp.wen.eq(1 << 1) yield yield wp.wen.eq(0) # part-port read yield rp1.ren.eq(1 << 1) yield - data = yield rp1.data_o + data = yield rp1.o_data print(data) assert data == 2 @@ -97,38 +97,38 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield rp1.ren.eq(1 << 5) yield rp2.ren.eq(1 << 1) yield wp.wen.eq(1 << 5) - yield wp.data_i.eq(6) + yield wp.i_data.eq(6) yield yield wp.wen.eq(0) yield rp1.ren.eq(0) yield rp2.ren.eq(0) - data1 = yield rp1.data_o + data1 = yield rp1.o_data print(data1) assert data1 == 6, data1 - data2 = yield rp2.data_o + data2 = yield rp2.o_data print(data2) assert data2 == 2, data2 yield - data = yield rp1.data_o + data = yield rp1.o_data print(data) # full port read (whole reg) yield dut.full_rd.ren.eq(0xff) yield yield dut.full_rd.ren.eq(0) - data = yield dut.full_rd.data_o + data = yield dut.full_rd.o_data print(hex(data)) # full port read (part reg) yield dut.full_rd.ren.eq(0x1 << 5) yield yield dut.full_rd.ren.eq(0) - data = yield dut.full_rd.data_o + data = yield dut.full_rd.o_data print(hex(data)) # full port part-write (part masked reg) yield dut.full_wr.wen.eq(0x1 << 1) - yield dut.full_wr.data_i.eq(0xe0) + yield dut.full_wr.i_data.eq(0xe0) yield yield dut.full_wr.wen.eq(0x0) @@ -136,12 +136,12 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield dut.full_rd.ren.eq(0xff) yield yield dut.full_rd.ren.eq(0) - data = yield dut.full_rd.data_o + data = yield dut.full_rd.o_data print(hex(data)) # full port write yield dut.full_wr.wen.eq(0xff) - yield dut.full_wr.data_i.eq(0xcafeface) + yield dut.full_wr.i_data.eq(0xcafeface) yield yield dut.full_wr.wen.eq(0x0) @@ -149,17 +149,17 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield dut.full_rd.ren.eq(0xff) yield yield dut.full_rd.ren.eq(0) - data = yield dut.full_rd.data_o + data = yield dut.full_rd.o_data print(hex(data)) # part write - yield wp.data_i.eq(2) + yield wp.i_data.eq(2) yield wp.wen.eq(1 << 1) yield yield wp.wen.eq(0) yield rp1.ren.eq(1 << 1) yield - data = yield rp1.data_o + data = yield rp1.o_data print(hex(data)) assert data == 2 @@ -167,7 +167,7 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield dut.full_rd.ren.eq(0xff) yield yield dut.full_rd.ren.eq(0) - data = yield dut.full_rd.data_o + data = yield dut.full_rd.o_data print(hex(data)) # simultaneous read/write: full-write, part-write, 3x part-read @@ -175,22 +175,22 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield rp2.ren.eq(1 << 1) yield rp3.ren.eq(1 << 3) yield wp.wen.eq(1 << 3) - yield wp.data_i.eq(6) + yield wp.i_data.eq(6) yield dut.full_wr.wen.eq((1 << 1) | (1 << 5)) - yield dut.full_wr.data_i.eq((0xa << (1*4)) | (0x3 << (5*4))) + yield dut.full_wr.i_data.eq((0xa << (1*4)) | (0x3 << (5*4))) yield yield dut.full_wr.wen.eq(0) yield wp.wen.eq(0) yield rp1.ren.eq(0) yield rp2.ren.eq(0) yield rp3.ren.eq(0) - data1 = yield rp1.data_o + data1 = yield rp1.o_data print(hex(data1)) assert data1 == 0x3 - data2 = yield rp2.data_o + data2 = yield rp2.o_data print(hex(data2)) assert data2 == 0xa - data3 = yield rp3.data_o + data3 = yield rp3.o_data print(hex(data3)) assert data3 == 0x6 diff --git a/src/soc/scoreboard/instruction_q.py b/src/soc/scoreboard/instruction_q.py index 4b256654..65182169 100644 --- a/src/soc/scoreboard/instruction_q.py +++ b/src/soc/scoreboard/instruction_q.py @@ -46,15 +46,15 @@ class InstructionQ(Elaboratable): self.n_out = n_out mqbits = (int(log(iqlen) / log(2))+2, False) - self.p_add_i = Signal(mqbits) # instructions to add (from data_i) + self.p_add_i = Signal(mqbits) # instructions to add (from i_data) self.p_o_ready = Signal() # instructions were added - self.data_i = Instruction._nq(n_in, "data_i") + self.i_data = Instruction._nq(n_in, "i_data") - self.data_o = Instruction._nq(n_out, "data_o") + self.o_data = Instruction._nq(n_out, "o_data") self.n_sub_i = Signal(mqbits) # number of instructions to remove self.n_sub_o = Signal(mqbits) # number of instructions removed - self.qsz = shape(self.data_o[0])[0] + self.qsz = shape(self.o_data[0])[0] q = [] for i in range(iqlen): q.append(Signal(self.qsz, name="q%d" % i)) @@ -97,7 +97,7 @@ class InstructionQ(Elaboratable): for i in range(self.n_out): opos = Signal(mqbits) comb += opos.eq(end_q + i) - comb += cat(self.data_o[i]).eq(self.q[opos]) + comb += cat(self.o_data[i]).eq(self.q[opos]) with m.If(self.n_sub_o): # ok now the end's moved @@ -109,7 +109,7 @@ class InstructionQ(Elaboratable): with m.If(self.p_add_i > Const(i, len(self.p_add_i))): ipos = Signal(mqbits) comb += ipos.eq(start_q + i) # should roll round - sync += self.q[ipos].eq(cat(self.data_i[i])) + sync += self.q[ipos].eq(cat(self.i_data[i])) sync += start_q.eq(start_q + self.p_add_i) with m.If(self.p_o_ready): @@ -126,11 +126,11 @@ class InstructionQ(Elaboratable): yield from self.q yield self.p_o_ready - for o in self.data_i: + for o in self.i_data: yield from list(o) yield self.p_add_i - for o in self.data_o: + for o in self.o_data: yield from list(o) yield self.n_sub_i yield self.n_sub_o diff --git a/src/soc/scoreboard/test_iq.py b/src/soc/scoreboard/test_iq.py index acd1b7af..d0131e94 100644 --- a/src/soc/scoreboard/test_iq.py +++ b/src/soc/scoreboard/test_iq.py @@ -28,8 +28,8 @@ class IQSim: print("sendlen", len(self.iq)-i, sendlen) for idx in range(sendlen): instr = self.iq[i+idx] - yield from eq(self.dut.data_i[idx], instr) - di = yield self.dut.data_i[idx] # .src1_i + yield from eq(self.dut.i_data[idx], instr) + di = yield self.dut.i_data[idx] # .src1_i print("senddata %d %x" % ((i+idx), di)) self.oq.append(di) yield self.dut.p_add_i.eq(sendlen) @@ -76,7 +76,7 @@ class IQSim: n_sub_o = yield self.dut.n_sub_o print("recv", n_sub_o) for j in range(n_sub_o): - r = yield self.dut.data_o[j] # .src1_i + r = yield self.dut.o_data[j] # .src1_i print("recvdata %x %s" % (r, repr(self.iq[i+j]))) assert r == self.oq[i+j] yield diff --git a/src/soc/scoreboard/test_mem2_fu_matrix.py b/src/soc/scoreboard/test_mem2_fu_matrix.py index 9fd84b24..dd5afc05 100644 --- a/src/soc/scoreboard/test_mem2_fu_matrix.py +++ b/src/soc/scoreboard/test_mem2_fu_matrix.py @@ -290,11 +290,11 @@ class Scoreboard(Elaboratable): # branch is active (TODO: a better signal: this is over-using the # go_write signal - actually the branch should not be "writing") with m.If(br1.go_wr_i): - sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2)) + sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2)) sync += bspec.active_i.eq(0) comb += bspec.br_i.eq(1) # branch occurs if data == 1, failed if data == 0 - comb += bspec.br_ok_i.eq(br1.data_o == 1) + comb += bspec.br_ok_i.eq(br1.o_data == 1) for i in range(n_intfus): # *expected* direction of the branch matched against *actual* comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i]) @@ -309,9 +309,9 @@ class Scoreboard(Elaboratable): comb += int_src2.ren.eq(intfus.src2_rsel_o) # connect ALUs to regfule - comb += int_dest.data_i.eq(cu.data_o) - comb += cu.src1_i.eq(int_src1.data_o) - comb += cu.src2_i.eq(int_src2.data_o) + comb += int_dest.i_data.eq(cu.o_data) + comb += cu.src1_i.eq(int_src1.o_data) + comb += cu.src2_i.eq(int_src2.o_data) # connect ALU Computation Units comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) diff --git a/src/soc/scoreboard/test_mem_fu_matrix.py b/src/soc/scoreboard/test_mem_fu_matrix.py index 949d0ff2..d02c3813 100644 --- a/src/soc/scoreboard/test_mem_fu_matrix.py +++ b/src/soc/scoreboard/test_mem_fu_matrix.py @@ -392,11 +392,11 @@ class Scoreboard(Elaboratable): # branch is active (TODO: a better signal: this is over-using the # go_write signal - actually the branch should not be "writing") with m.If(br1.go_wr_i): - sync += self.branch_direction_o.eq(br1.data_o+Const(1, 2)) + sync += self.branch_direction_o.eq(br1.o_data+Const(1, 2)) sync += bspec.active_i.eq(0) comb += bspec.br_i.eq(1) # branch occurs if data == 1, failed if data == 0 - comb += bspec.br_ok_i.eq(br1.data_o == 1) + comb += bspec.br_ok_i.eq(br1.o_data == 1) for i in range(n_intfus): # *expected* direction of the branch matched against *actual* comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i]) @@ -411,9 +411,9 @@ class Scoreboard(Elaboratable): comb += int_src2.ren.eq(intfus.src2_rsel_o) # connect ALUs to regfule - comb += int_dest.data_i.eq(cu.data_o) - comb += cu.src1_i.eq(int_src1.data_o) - comb += cu.src2_i.eq(int_src2.data_o) + comb += int_dest.i_data.eq(cu.o_data) + comb += cu.src1_i.eq(int_src1.o_data) + comb += cu.src2_i.eq(int_src2.o_data) # connect ALU Computation Units comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index e9eb1a18..2e5fa5bd 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -48,7 +48,7 @@ from nmutil.util import rising_edge # helper function for reducing a list of signals down to a parallel # ORed single signal. -def ortreereduce(tree, attr="data_o"): +def ortreereduce(tree, attr="o_data"): return treereduce(tree, operator.or_, lambda x: getattr(x, attr)) @@ -338,9 +338,9 @@ class NonProductionCore(Elaboratable): src = fu.src_i[idx] print("reg connect widths", regfile, regname, pi, funame, - src.shape(), rport.data_o.shape()) + src.shape(), rport.o_data.shape()) # all FUs connect to same port - comb += src.eq(rport.data_o) + comb += src.eq(rport.o_data) # or-reduce the muxed read signals if rfile.unary: @@ -466,11 +466,11 @@ class NonProductionCore(Elaboratable): # connect regfile port to input print("reg connect widths", regfile, regname, pi, funame, - dest.shape(), wport.data_i.shape()) + dest.shape(), wport.i_data.shape()) wsigs.append(fu_dest_latch) # here is where we create the Write Broadcast Bus. simple, eh? - comb += wport.data_i.eq(ortreereduce_sig(wsigs)) + comb += wport.i_data.eq(ortreereduce_sig(wsigs)) if rfile.unary: # for unary-addressed comb += wport.wen.eq(ortreereduce_sig(wens)) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 5d5c1ff2..5c40b3c9 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -73,7 +73,7 @@ def state_get(m, core_rst, state_i, name, regfile, regnum): comb += regfile.ren.eq(1<= cur_vl)): # end of VL loop. Update PC and reset src/dst step comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) - comb += self.state_w_pc.data_i.eq(nia) + comb += self.state_w_pc.i_data.eq(nia) comb += new_svstate.srcstep.eq(0) comb += new_svstate.dststep.eq(0) comb += update_svstate.eq(1) @@ -804,7 +804,7 @@ class TestIssuerInternal(Elaboratable): # TODO: this just blithely overwrites whatever # pipeline updated the PC comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) - comb += self.state_w_pc.data_i.eq(nia) + comb += self.state_w_pc.i_data.eq(nia) # reset SRCSTEP before returning to Fetch if self.svp64_en: with m.If(pdecode2.loop_continue): @@ -830,7 +830,7 @@ class TestIssuerInternal(Elaboratable): # while stopped, allow updating the PC and SVSTATE with m.If(self.pc_i.ok): comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) - comb += self.state_w_pc.data_i.eq(self.pc_i.data) + comb += self.state_w_pc.i_data.eq(self.pc_i.data) sync += pc_changed.eq(1) with m.If(self.svstate_i.ok): comb += new_svstate.eq(self.svstate_i.data) @@ -840,7 +840,7 @@ class TestIssuerInternal(Elaboratable): # check if svstate needs updating: if so, write it to State Regfile with m.If(update_svstate): comb += self.state_w_sv.wen.eq(1<