From e62b4753810c953d7b8a002621576e776a9518d6 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 9 May 2020 10:57:31 -0400 Subject: [PATCH] Add right shift test to test_caller.py --- src/soc/decoder/isa/test_caller.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 467d6d21..7e5534a6 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -187,7 +187,7 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program) self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64)) - def test_shift(self): + def test_slw(self): lst = ["slw 1, 3, 2"] initial_regs = [0] * 32 initial_regs[3] = 0xdeadbeefcafebabe @@ -196,6 +196,15 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs) self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32)) + def test_srw(self): + lst = ["srw 1, 3, 2"] + initial_regs = [0] * 32 + initial_regs[3] = 0xdeadbeefcafebabe + initial_regs[2] = 5 + with Program(lst) as program: + sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 32)) + def test_mtcrf(self): for i in range(4): # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for -- 2.30.2