From e62b6fed2a6f2b9ad70cf8aae1c411f71d9ad2bb Mon Sep 17 00:00:00 2001 From: David Taylor Date: Mon, 8 Jun 1998 19:18:21 +0000 Subject: [PATCH] add test to verify that changes made to the PSW in-parallel-with a trap instruction end up in the bPSW and not in the PSW. (PR 16026). --- sim/testsuite/d30v-elf/trap.S | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 sim/testsuite/d30v-elf/trap.S diff --git a/sim/testsuite/d30v-elf/trap.S b/sim/testsuite/d30v-elf/trap.S new file mode 100644 index 00000000000..08399f9d21a --- /dev/null +++ b/sim/testsuite/d30v-elf/trap.S @@ -0,0 +1,35 @@ +# verify that trap || cmp works + add r8,r0,0x11223344 ; + add r9,r0,0x11223344 ; + + mvtsys bpsw,r0 || nop + mvtsys bpc,r0 || nop + + add r1,r0,0x97000555 ; for psw + mvtsys psw,r1 || nop + trap 0 || cmpeq f0,r8,r9,; + + .long 0x0e000004, 0x00f00000 + + .section .eit_v, "a" + nop || nop + nop || nop + nop || nop + nop || nop + +# save the old bpsw, psw + mvfsys r4,bpsw || nop + mvfsys r5,psw || nop + +# load up what they should be + add r6,r0,0x97004555 + add r7,r0,0x90000000 + +# verify that they have the right values +# return exit value in r2 -- 0 success, 47 failure + add r2,r0,47 + cmpeq f0,r4,r6 || nop + cmpeq f1,r5,r7 || nop + add/tt r2,r0,r0 || nop + + reit -- 2.30.2