From e62db39c0a172d4d3690ea98b711dfdd65dad42e Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Sun, 19 Jan 1997 17:17:16 -0500 Subject: [PATCH] (rot[lr][shq]i3): Allow 'N', 'O' or 'P' operands. From-SVN: r13524 --- gcc/config/m68k/m68k.md | 67 +++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 2244adff18b..877f4423cab 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -64,6 +64,9 @@ ;;- 'K' all integers EXCEPT -128 .. 127 ;;- 'L' -8 .. -1 ;;- 'M' all integers EXCEPT -256 .. 255 +;;- 'N' 24 .. 31 +;;- 'O' 16 +;;- 'P' 8 .. 15 ;;- Assembler specs: ;;- "%." size separator ("." or "") move%.l d0,d1 @@ -4712,38 +4715,84 @@ (define_insn "rotlsi3" [(set (match_operand:SI 0 "register_operand" "=d") (rotate:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "general_operand" "dI")))] + (match_operand:SI 2 "general_operand" "dINO")))] "!TARGET_5200" - "rol%.l %2,%0") + "* +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16) + return \"swap %0\"; + else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16) + { + INTVAL (operands[2]) = 32 - INTVAL (operands[2]); + return \"ror%.l %2,%0\"; + } + else + return \"rol%.l %2,%0\"; +}") (define_insn "rotlhi3" [(set (match_operand:HI 0 "register_operand" "=d") (rotate:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "general_operand" "dI")))] + (match_operand:HI 2 "general_operand" "dIP")))] "!TARGET_5200" - "rol%.w %2,%0") - + "* +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) + { + INTVAL (operands[2]) = 16 - INTVAL (operands[2]); + return \"ror%.w %2,%0\"; + } + else + return \"rol%.w %2,%0\"; +}") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotate:HI (match_dup 0) - (match_operand:HI 1 "general_operand" "dI")))] + (match_operand:HI 1 "general_operand" "dIP")))] "!TARGET_5200" - "rol%.w %1,%0") + "* +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) + { + INTVAL (operands[2]) = 16 - INTVAL (operands[2]); + return \"ror%.w %2,%0\"; + } + else + return \"rol%.w %2,%0\"; +}") (define_insn "rotlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (rotate:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] "!TARGET_5200" - "rol%.b %2,%0") + "* +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) + { + INTVAL (operands[2]) = 8 - INTVAL (operands[2]); + return \"ror%.b %2,%0\"; + } + else + return \"rol%.b %2,%0\"; +}") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotate:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] "!TARGET_5200" - "rol%.b %1,%0") + "* +{ + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) + { + INTVAL (operands[2]) = 8 - INTVAL (operands[2]); + return \"ror%.b %2,%0\"; + } + else + return \"rol%.b %2,%0\"; +}") (define_insn "rotrsi3" [(set (match_operand:SI 0 "register_operand" "=d") -- 2.30.2