From e6387ded371ff4be47801a43d17e42e2a3923f8c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 21 Jan 2021 03:10:40 -0800 Subject: [PATCH] arch-riscv: Stop "using namespace std" Change-Id: Ia18ac69797019fb853b7c07a3961840ee6b0df39 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39558 Reviewed-by: Daniel Carvalho Maintainer: Gabe Black Tested-by: kokoro --- src/arch/riscv/insts/amo.cc | 30 +- src/arch/riscv/insts/mem.cc | 10 +- src/arch/riscv/insts/standard.cc | 16 +- src/arch/riscv/isa/decoder.isa | 348 ++++++++++++------------ src/arch/riscv/isa/formats/fp.isa | 8 +- src/arch/riscv/isa/formats/standard.isa | 13 +- src/arch/riscv/isa/includes.isa | 2 - src/arch/riscv/process.cc | 27 +- src/arch/riscv/remote_gdb.cc | 1 - src/arch/riscv/tlb.cc | 5 +- 10 files changed, 227 insertions(+), 233 deletions(-) diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc index 0b54bb05d..305cee81e 100644 --- a/src/arch/riscv/insts/amo.cc +++ b/src/arch/riscv/insts/amo.cc @@ -37,17 +37,15 @@ #include "cpu/exec_context.hh" #include "cpu/static_inst.hh" -using namespace std; - namespace RiscvISA { // memfence micro instruction -string +std::string MemFenceMicro::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; return ss.str(); } @@ -59,11 +57,11 @@ Fault MemFenceMicro::execute(ExecContext *xc, } // load-reserved -string +std::string LoadReserved::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic; if (AQ || RL) ss << '_'; @@ -76,22 +74,22 @@ LoadReserved::generateDisassembly( return ss.str(); } -string +std::string LoadReservedMicro::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", (" << registerName(srcRegIdx(0)) << ')'; return ss.str(); } // store-conditional -string +std::string StoreCond::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic; if (AQ || RL) ss << '_'; @@ -105,11 +103,11 @@ StoreCond::generateDisassembly( return ss.str(); } -string +std::string StoreCondMicro::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " << registerName(srcRegIdx(1)) << ", (" << registerName(srcRegIdx(0)) << ')'; @@ -117,11 +115,11 @@ StoreCondMicro::generateDisassembly( } // AMOs -string +std::string AtomicMemOp::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic; if (AQ || RL) ss << '_'; @@ -135,11 +133,11 @@ AtomicMemOp::generateDisassembly( return ss.str(); } -string +std::string AtomicMemOpMicro::generateDisassembly( Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " << registerName(srcRegIdx(1)) << ", (" << registerName(srcRegIdx(0)) << ')'; diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc index dde330a68..383ba9635 100644 --- a/src/arch/riscv/insts/mem.cc +++ b/src/arch/riscv/insts/mem.cc @@ -37,24 +37,22 @@ #include "arch/riscv/utility.hh" #include "cpu/static_inst.hh" -using namespace std; - namespace RiscvISA { -string +std::string Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " << offset << '(' << registerName(srcRegIdx(0)) << ')'; return ss.str(); } -string +std::string Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " << offset << '(' << registerName(srcRegIdx(0)) << ')'; return ss.str(); diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc index c04dae63e..edc1916b5 100644 --- a/src/arch/riscv/insts/standard.cc +++ b/src/arch/riscv/insts/standard.cc @@ -37,15 +37,13 @@ #include "arch/riscv/utility.hh" #include "cpu/static_inst.hh" -using namespace std; - namespace RiscvISA { -string +std::string RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " << registerName(srcRegIdx(0)); if (_numSrcRegs >= 2) @@ -55,16 +53,16 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const return ss.str(); } -string +std::string CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "; auto data = CSRData.find(csr); if (data != CSRData.end()) ss << data->second.name; else - ss << "?? (" << hex << "0x" << csr << dec << ")"; + ss << "?? (" << std::hex << "0x" << csr << std::dec << ")"; if (_numSrcRegs > 0) ss << ", " << registerName(srcRegIdx(0)); else @@ -72,11 +70,11 @@ CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const return ss.str(); } -string +std::string SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const { if (strcmp(mnemonic, "fence_vma") == 0) { - stringstream ss; + std::stringstream ss; ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " << registerName(srcRegIdx(1)); return ss.str(); diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 5ef68fe1f..b7e316122 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -42,8 +42,8 @@ decode QUADRANT default Unknown::unknown() { CIMM8<5:2> << 6; }}, {{ if (machInst == 0) - fault = make_shared("zero instruction", - machInst); + fault = std::make_shared("zero instruction", + machInst); Rp2 = sp + imm; }}, uint64_t); format CompressedLoad { @@ -52,8 +52,8 @@ decode QUADRANT default Unknown::unknown() { }}, {{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + fault = std::make_shared("FPU is off", + machInst); Fp2_bits = Mem; }}, {{ @@ -82,8 +82,8 @@ decode QUADRANT default Unknown::unknown() { }}, {{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + fault = std::make_shared("FPU is off", + machInst); Mem = Fp2_bits; }}, {{ @@ -116,11 +116,11 @@ decode QUADRANT default Unknown::unknown() { }}, {{ if ((RC1 == 0) != (imm == 0)) { if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } else // imm == 0 - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } Rc1_sd = Rc1_sd + imm; }}); @@ -130,8 +130,8 @@ decode QUADRANT default Unknown::unknown() { imm |= ~((uint64_t)0x1F); }}, {{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1_sd = (int32_t)Rc1_sd + imm; }}); @@ -141,8 +141,8 @@ decode QUADRANT default Unknown::unknown() { imm |= ~((uint64_t)0x1F); }}, {{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1_sd = imm; }}); @@ -156,8 +156,8 @@ decode QUADRANT default Unknown::unknown() { imm |= ~((int64_t)0x1FF); }}, {{ if (imm == 0) { - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } sp_sd = sp_sd + imm; }}); @@ -167,12 +167,12 @@ decode QUADRANT default Unknown::unknown() { imm |= ~((uint64_t)0x1FFFF); }}, {{ if (RC1 == 0 || RC1 == 2) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } if (imm == 0) { - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } Rc1_sd = imm; }}); @@ -184,8 +184,8 @@ decode QUADRANT default Unknown::unknown() { imm = CIMM5 | (CIMM1 << 5); }}, {{ if (imm == 0) { - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } Rp1 = Rp1 >> imm; }}, uint64_t); @@ -193,8 +193,8 @@ decode QUADRANT default Unknown::unknown() { imm = CIMM5 | (CIMM1 << 5); }}, {{ if (imm == 0) { - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } Rp1_sd = Rp1_sd >> imm; }}, uint64_t); @@ -256,12 +256,12 @@ decode QUADRANT default Unknown::unknown() { imm = CIMM5 | (CIMM1 << 5); }}, {{ if (imm == 0) { - fault = make_shared("immediate = 0", - machInst); + fault = std::make_shared( + "immediate = 0", machInst); } if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1 = Rc1 << imm; }}, uint64_t); @@ -281,8 +281,8 @@ decode QUADRANT default Unknown::unknown() { CIMM5<1:0> << 6; }}, {{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1_sd = Mem_sw; }}, {{ @@ -294,8 +294,8 @@ decode QUADRANT default Unknown::unknown() { CIMM5<2:0> << 6; }}, {{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1_sd = Mem_sd; }}, {{ @@ -306,15 +306,15 @@ decode QUADRANT default Unknown::unknown() { 0x0: decode RC2 { 0x0: Jump::c_jr({{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } NPC = Rc1; }}, IsIndirectControl, IsUncondControl, IsCall); default: CROp::c_mv({{ if (RC1 == 0) { - fault = make_shared("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } Rc1 = Rc2; }}); @@ -322,17 +322,16 @@ decode QUADRANT default Unknown::unknown() { 0x1: decode RC1 { 0x0: SystemOp::c_ebreak({{ if (RC2 != 0) { - fault = make_shared("source reg x1", - machInst); + fault = std::make_shared( + "source reg x1", machInst); } - fault = make_shared(xc->pcState()); + fault = std::make_shared(xc->pcState()); }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); default: decode RC2 { 0x0: Jump::c_jalr({{ if (RC1 == 0) { - fault = make_shared - ("source reg x0", - machInst); + fault = std::make_shared( + "source reg x0", machInst); } ra = NPC; NPC = Rc1; @@ -401,17 +400,18 @@ decode QUADRANT default Unknown::unknown() { format Load { 0x2: flw({{ STATUS status = xc->readMiscReg(MISCREG_STATUS); - if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + if (status.fs == FPUStatus::OFF) { + fault = std::make_shared( + "FPU is off", machInst); + } Fd_bits = (uint64_t)Mem_uw; }}, inst_flags=FloatMemReadOp); 0x3: fld({{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + fault = std::make_shared( + "FPU is off", machInst); Fd_bits = Mem; }}, inst_flags=FloatMemReadOp); @@ -506,16 +506,16 @@ decode QUADRANT default Unknown::unknown() { 0x2: fsw({{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + fault = std::make_shared( + "FPU is off", machInst); Mem_uw = (uint32_t)Fs2_bits; }}, inst_flags=FloatMemWriteOp); 0x3: fsd({{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", - machInst); + fault = std::make_shared( + "FPU is off", machInst); Mem_ud = Fs2_bits; }}, inst_flags=FloatMemWriteOp); @@ -762,9 +762,10 @@ decode QUADRANT default Unknown::unknown() { 0x1: div({{ if (Rs2_sd == 0) { Rd_sd = -1; - } else if (Rs1_sd == numeric_limits::min() + } else if ( + Rs1_sd == std::numeric_limits::min() && Rs2_sd == -1) { - Rd_sd = numeric_limits::min(); + Rd_sd = std::numeric_limits::min(); } else { Rd_sd = Rs1_sd/Rs2_sd; } @@ -776,7 +777,7 @@ decode QUADRANT default Unknown::unknown() { }}); 0x1: divu({{ if (Rs2 == 0) { - Rd = numeric_limits::max(); + Rd = std::numeric_limits::max(); } else { Rd = Rs1/Rs2; } @@ -792,7 +793,8 @@ decode QUADRANT default Unknown::unknown() { 0x1: rem({{ if (Rs2_sd == 0) { Rd = Rs1_sd; - } else if (Rs1_sd == numeric_limits::min() + } else if ( + Rs1_sd == std::numeric_limits::min() && Rs2_sd == -1) { Rd = 0; } else { @@ -838,9 +840,9 @@ decode QUADRANT default Unknown::unknown() { 0x4: divw({{ if (Rs2_sw == 0) { Rd_sd = -1; - } else if (Rs1_sw == numeric_limits::min() + } else if (Rs1_sw == std::numeric_limits::min() && Rs2_sw == -1) { - Rd_sd = numeric_limits::min(); + Rd_sd = std::numeric_limits::min(); } else { Rd_sd = Rs1_sw/Rs2_sw; } @@ -851,7 +853,7 @@ decode QUADRANT default Unknown::unknown() { }}); 0x1: divuw({{ if (Rs2_uw == 0) { - Rd_sd = numeric_limits::max(); + Rd_sd = std::numeric_limits::max(); } else { Rd_sd = (int32_t)(Rs1_uw/Rs2_uw); } @@ -863,7 +865,7 @@ decode QUADRANT default Unknown::unknown() { 0x6: remw({{ if (Rs2_sw == 0) { Rd_sd = Rs1_sw; - } else if (Rs1_sw == numeric_limits::min() + } else if (Rs1_sw == std::numeric_limits::min() && Rs2_sw == -1) { Rd_sd = 0; } else { @@ -895,15 +897,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(fs3)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(fs1) || std::isinf(fs2) || std::isinf(fs3)) { - if (signbit(fs1) == signbit(fs2) + if (std::signbit(fs1) == std::signbit(fs2) && !std::isinf(fs3)) { - fd = numeric_limits::infinity(); - } else if (signbit(fs1) != signbit(fs2) + fd = std::numeric_limits::infinity(); + } else if (std::signbit(fs1) != std::signbit(fs2) && !std::isinf(fs3)) { - fd = -numeric_limits::infinity(); + fd = -std::numeric_limits::infinity(); } else { // Fs3_sf is infinity fd = fs3; } @@ -919,15 +921,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(Fs3)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(Fs1) || std::isinf(Fs2) || std::isinf(Fs3)) { - if (signbit(Fs1) == signbit(Fs2) + if (std::signbit(Fs1) == std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = numeric_limits::infinity(); - } else if (signbit(Fs1) != signbit(Fs2) + Fd = std::numeric_limits::infinity(); + } else if (std::signbit(Fs1) != std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = -numeric_limits::infinity(); + Fd = -std::numeric_limits::infinity(); } else { Fd = Fs3; } @@ -950,15 +952,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(fs3)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(fs1) || std::isinf(fs2) || std::isinf(fs3)) { - if (signbit(fs1) == signbit(fs2) + if (std::signbit(fs1) == std::signbit(fs2) && !std::isinf(fs3)) { - fd = numeric_limits::infinity(); - } else if (signbit(fs1) != signbit(fs2) + fd = std::numeric_limits::infinity(); + } else if (std::signbit(fs1) != std::signbit(fs2) && !std::isinf(fs3)) { - fd = -numeric_limits::infinity(); + fd = -std::numeric_limits::infinity(); } else { // Fs3_sf is infinity fd = -fs3; } @@ -974,15 +976,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(Fs3)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(Fs1) || std::isinf(Fs2) || std::isinf(Fs3)) { - if (signbit(Fs1) == signbit(Fs2) + if (std::signbit(Fs1) == std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = numeric_limits::infinity(); - } else if (signbit(Fs1) != signbit(Fs2) + Fd = std::numeric_limits::infinity(); + } else if (std::signbit(Fs1) != std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = -numeric_limits::infinity(); + Fd = -std::numeric_limits::infinity(); } else { Fd = -Fs3; } @@ -1005,15 +1007,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(fs3)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(fs1) || std::isinf(fs2) || std::isinf(fs3)) { - if (signbit(fs1) == signbit(fs2) + if (std::signbit(fs1) == std::signbit(fs2) && !std::isinf(fs3)) { - fd = -numeric_limits::infinity(); - } else if (signbit(fs1) != signbit(fs2) + fd = -std::numeric_limits::infinity(); + } else if (std::signbit(fs1) != std::signbit(fs2) && !std::isinf(fs3)) { - fd = numeric_limits::infinity(); + fd = std::numeric_limits::infinity(); } else { // Fs3_sf is infinity fd = fs3; } @@ -1029,15 +1031,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(Fs3)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(Fs1) || std::isinf(Fs2) || std::isinf(Fs3)) { - if (signbit(Fs1) == signbit(Fs2) + if (std::signbit(Fs1) == std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = -numeric_limits::infinity(); - } else if (signbit(Fs1) != signbit(Fs2) + Fd = -std::numeric_limits::infinity(); + } else if (std::signbit(Fs1) != std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = numeric_limits::infinity(); + Fd = std::numeric_limits::infinity(); } else { Fd = Fs3; } @@ -1060,15 +1062,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(fs3)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(fs1) || std::isinf(fs2) || std::isinf(fs3)) { - if (signbit(fs1) == signbit(fs2) + if (std::signbit(fs1) == std::signbit(fs2) && !std::isinf(fs3)) { - fd = -numeric_limits::infinity(); - } else if (signbit(fs1) != signbit(fs2) + fd = -std::numeric_limits::infinity(); + } else if (std::signbit(fs1) != std::signbit(fs2) && !std::isinf(fs3)) { - fd = numeric_limits::infinity(); + fd = std::numeric_limits::infinity(); } else { // Fs3_sf is infinity fd = -fs3; } @@ -1084,15 +1086,15 @@ decode QUADRANT default Unknown::unknown() { || issignalingnan(Fs3)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else if (std::isinf(Fs1) || std::isinf(Fs2) || std::isinf(Fs3)) { - if (signbit(Fs1) == signbit(Fs2) + if (std::signbit(Fs1) == std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = -numeric_limits::infinity(); - } else if (signbit(Fs1) != signbit(Fs2) + Fd = -std::numeric_limits::infinity(); + } else if (std::signbit(Fs1) != std::signbit(Fs2) && !std::isinf(Fs3)) { - Fd = numeric_limits::infinity(); + Fd = std::numeric_limits::infinity(); } else { Fd = -Fs3; } @@ -1112,7 +1114,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(fs1) || issignalingnan(fs2)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else { fd = fs1 + fs2; } @@ -1123,7 +1125,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(Fs1) || issignalingnan(Fs2)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else { Fd = Fs1 + Fs2; } @@ -1138,7 +1140,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(fs1) || issignalingnan(fs2)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else { fd = fs1 - fs2; } @@ -1149,7 +1151,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(Fs1) || issignalingnan(Fs2)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else { Fd = Fs1 - Fs2; } @@ -1164,7 +1166,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(fs1) || issignalingnan(fs2)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else { fd = fs1*fs2; } @@ -1175,7 +1177,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(Fs1) || issignalingnan(Fs2)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else { Fd = Fs1*Fs2; } @@ -1190,7 +1192,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(fs1) || issignalingnan(fs2)) { FFLAGS |= FloatInvalid; } - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); } else { fd = fs1/fs2; } @@ -1201,7 +1203,7 @@ decode QUADRANT default Unknown::unknown() { if (issignalingnan(Fs1) || issignalingnan(Fs2)) { FFLAGS |= FloatInvalid; } - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); } else { Fd = Fs1/Fs2; } @@ -1214,7 +1216,7 @@ decode QUADRANT default Unknown::unknown() { float fd; if (issignalingnan(fs1)) { - fd = numeric_limits::signaling_NaN(); + fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { fd = copysign(fs1, fs2); @@ -1228,7 +1230,7 @@ decode QUADRANT default Unknown::unknown() { float fd; if (issignalingnan(fs1)) { - fd = numeric_limits::signaling_NaN(); + fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { fd = copysign(fs1, -fs2); @@ -1242,10 +1244,10 @@ decode QUADRANT default Unknown::unknown() { float fd; if (issignalingnan(fs1)) { - fd = numeric_limits::signaling_NaN(); + fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { - fd = fs1*(signbit(fs2) ? -1.0 : 1.0); + fd = fs1*(std::signbit(fs2) ? -1.0 : 1.0); } Fd_bits = (uint64_t)reinterpret_cast(fd); }}, FloatMiscOp); @@ -1253,7 +1255,7 @@ decode QUADRANT default Unknown::unknown() { 0x11: decode ROUND_MODE { 0x0: fsgnj_d({{ if (issignalingnan(Fs1)) { - Fd = numeric_limits::signaling_NaN(); + Fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { Fd = copysign(Fs1, Fs2); @@ -1261,7 +1263,7 @@ decode QUADRANT default Unknown::unknown() { }}, FloatMiscOp); 0x1: fsgnjn_d({{ if (issignalingnan(Fs1)) { - Fd = numeric_limits::signaling_NaN(); + Fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { Fd = copysign(Fs1, -Fs2); @@ -1269,10 +1271,10 @@ decode QUADRANT default Unknown::unknown() { }}, FloatMiscOp); 0x2: fsgnjx_d({{ if (issignalingnan(Fs1)) { - Fd = numeric_limits::signaling_NaN(); + Fd = std::numeric_limits::signaling_NaN(); feclearexcept(FE_INVALID); } else { - Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0); + Fd = Fs1*(std::signbit(Fs2) ? -1.0 : 1.0); } }}, FloatMiscOp); } @@ -1338,12 +1340,12 @@ decode QUADRANT default Unknown::unknown() { } 0x20: fcvt_s_d({{ if (CONV_SGN != 1) { - fault = make_shared("CONV_SGN != 1", - machInst); + fault = std::make_shared( + "CONV_SGN != 1", machInst); } float fd; if (issignalingnan(Fs1)) { - fd = numeric_limits::quiet_NaN(); + fd = std::numeric_limits::quiet_NaN(); FFLAGS |= FloatInvalid; } else { fd = (float)Fs1; @@ -1352,14 +1354,14 @@ decode QUADRANT default Unknown::unknown() { }}, FloatCvtOp); 0x21: fcvt_d_s({{ if (CONV_SGN != 0) { - fault = make_shared("CONV_SGN != 0", - machInst); + fault = std::make_shared( + "CONV_SGN != 0", machInst); } uint32_t temp; float fs1 = reinterpret_cast(temp = Fs1_bits); if (issignalingnan(fs1)) { - Fd = numeric_limits::quiet_NaN(); + Fd = std::numeric_limits::quiet_NaN(); FFLAGS |= FloatInvalid; } else { Fd = (double)fs1; @@ -1367,8 +1369,8 @@ decode QUADRANT default Unknown::unknown() { }}, FloatCvtOp); 0x2c: fsqrt_s({{ if (RS2 != 0) { - fault = make_shared("source reg x1", - machInst); + fault = std::make_shared( + "source reg x1", machInst); } uint32_t temp; float fs1 = reinterpret_cast(temp = Fs1_bits); @@ -1382,8 +1384,8 @@ decode QUADRANT default Unknown::unknown() { }}, FloatSqrtOp); 0x2d: fsqrt_d({{ if (RS2 != 0) { - fault = make_shared("source reg x1", - machInst); + fault = std::make_shared( + "source reg x1", machInst); } Fd = sqrt(Fs1); }}, FloatSqrtOp); @@ -1453,15 +1455,15 @@ decode QUADRANT default Unknown::unknown() { float fs1 = reinterpret_cast(temp = Fs1_bits); if (std::isnan(fs1)) { - Rd_sd = numeric_limits::max(); + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 >= - float(numeric_limits::max())) { - Rd_sd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 <= - float(numeric_limits::min())) { - Rd_sd = numeric_limits::min(); + float(std::numeric_limits::min())) { + Rd_sd = std::numeric_limits::min(); FFLAGS |= FloatInvalid; } else { Rd_sd = (int32_t)fs1; @@ -1472,14 +1474,14 @@ decode QUADRANT default Unknown::unknown() { float fs1 = reinterpret_cast(temp = Fs1_bits); if (std::isnan(fs1)) { - Rd = numeric_limits::max(); + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 < 0.0) { Rd = 0; FFLAGS |= FloatInvalid; } else if (fs1 > - float(numeric_limits::max())) { - Rd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else { Rd = (uint32_t)fs1; @@ -1490,15 +1492,15 @@ decode QUADRANT default Unknown::unknown() { float fs1 = reinterpret_cast(temp = Fs1_bits); if (std::isnan(fs1)) { - Rd_sd = numeric_limits::max(); + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 > - float(numeric_limits::max())) { - Rd_sd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 < - float(numeric_limits::min())) { - Rd_sd = numeric_limits::min(); + float(std::numeric_limits::min())) { + Rd_sd = std::numeric_limits::min(); FFLAGS |= FloatInvalid; } else { Rd_sd = (int64_t)fs1; @@ -1509,14 +1511,14 @@ decode QUADRANT default Unknown::unknown() { float fs1 = reinterpret_cast(temp = Fs1_bits); if (std::isnan(fs1)) { - Rd = numeric_limits::max(); + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (fs1 < 0.0) { Rd = 0; FFLAGS |= FloatInvalid; } else if (fs1 > - float(numeric_limits::max())) { - Rd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else { Rd = (uint64_t)fs1; @@ -1526,15 +1528,15 @@ decode QUADRANT default Unknown::unknown() { 0x61: decode CONV_SGN { 0x0: fcvt_w_d({{ if (std::isnan(Fs1)) { - Rd_sd = numeric_limits::max(); + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 > - float(numeric_limits::max())) { - Rd_sd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 < - float(numeric_limits::min())) { - Rd_sd = numeric_limits::min(); + float(std::numeric_limits::min())) { + Rd_sd = std::numeric_limits::min(); FFLAGS |= FloatInvalid; } else { Rd_sd = (int32_t)Fs1; @@ -1542,14 +1544,14 @@ decode QUADRANT default Unknown::unknown() { }}, FloatCvtOp); 0x1: fcvt_wu_d({{ if (std::isnan(Fs1)) { - Rd = numeric_limits::max(); + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 < 0) { Rd = 0; FFLAGS |= FloatInvalid; } else if (Fs1 > - float(numeric_limits::max())) { - Rd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else { Rd = (uint32_t)Fs1; @@ -1557,15 +1559,15 @@ decode QUADRANT default Unknown::unknown() { }}, FloatCvtOp); 0x2: fcvt_l_d({{ if (std::isnan(Fs1)) { - Rd_sd = numeric_limits::max(); + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 > - float(numeric_limits::max())) { - Rd_sd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd_sd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 < - float(numeric_limits::min())) { - Rd_sd = numeric_limits::min(); + float(std::numeric_limits::min())) { + Rd_sd = std::numeric_limits::min(); FFLAGS |= FloatInvalid; } else { Rd_sd = Fs1; @@ -1573,14 +1575,14 @@ decode QUADRANT default Unknown::unknown() { }}, FloatCvtOp); 0x3: fcvt_lu_d({{ if (std::isnan(Fs1)) { - Rd = numeric_limits::max(); + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else if (Fs1 < 0) { Rd = 0; FFLAGS |= FloatInvalid; } else if (Fs1 > - float(numeric_limits::max())) { - Rd = numeric_limits::max(); + float(std::numeric_limits::max())) { + Rd = std::numeric_limits::max(); FFLAGS |= FloatInvalid; } else { Rd = Fs1; @@ -1629,9 +1631,9 @@ decode QUADRANT default Unknown::unknown() { 0x1: fclass_s({{ uint32_t temp; float fs1 = reinterpret_cast(temp = Fs1_bits); - switch (fpclassify(fs1)) { + switch (std::fpclassify(fs1)) { case FP_INFINITE: - if (signbit(fs1)) { + if (std::signbit(fs1)) { Rd = 1 << 0; } else { Rd = 1 << 7; @@ -1645,21 +1647,21 @@ decode QUADRANT default Unknown::unknown() { } break; case FP_ZERO: - if (signbit(fs1)) { + if (std::signbit(fs1)) { Rd = 1 << 3; } else { Rd = 1 << 4; } break; case FP_SUBNORMAL: - if (signbit(fs1)) { + if (std::signbit(fs1)) { Rd = 1 << 2; } else { Rd = 1 << 5; } break; case FP_NORMAL: - if (signbit(fs1)) { + if (std::signbit(fs1)) { Rd = 1 << 1; } else { Rd = 1 << 6; @@ -1676,9 +1678,9 @@ decode QUADRANT default Unknown::unknown() { Rd = Fs1_bits; }}, FloatCvtOp); 0x1: fclass_d({{ - switch (fpclassify(Fs1)) { + switch (std::fpclassify(Fs1)) { case FP_INFINITE: - if (signbit(Fs1)) { + if (std::signbit(Fs1)) { Rd = 1 << 0; } else { Rd = 1 << 7; @@ -1692,21 +1694,21 @@ decode QUADRANT default Unknown::unknown() { } break; case FP_ZERO: - if (signbit(Fs1)) { + if (std::signbit(Fs1)) { Rd = 1 << 3; } else { Rd = 1 << 4; } break; case FP_SUBNORMAL: - if (signbit(Fs1)) { + if (std::signbit(Fs1)) { Rd = 1 << 2; } else { Rd = 1 << 5; } break; case FP_NORMAL: - if (signbit(Fs1)) { + if (std::signbit(Fs1)) { Rd = 1 << 1; } else { Rd = 1 << 6; @@ -1791,12 +1793,12 @@ decode QUADRANT default Unknown::unknown() { 0x0: decode FUNCT7 { 0x0: decode RS2 { 0x0: ecall({{ - fault = make_shared( + fault = std::make_shared( (PrivilegeMode)xc->readMiscReg(MISCREG_PRV)); }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass); 0x1: ebreak({{ - fault = make_shared( + fault = std::make_shared( xc->pcState()); }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 0x2: uret({{ @@ -1814,7 +1816,7 @@ decode QUADRANT default Unknown::unknown() { MISCREG_PRV); if (pm == PRV_U || (pm == PRV_S && status.tsr == 1)) { - fault = make_shared( + fault = std::make_shared( "sret in user mode or TSR enabled", machInst); NPC = NPC; @@ -1833,7 +1835,7 @@ decode QUADRANT default Unknown::unknown() { MISCREG_PRV); if (pm == PRV_U || (pm == PRV_S && status.tw == 1)) { - fault = make_shared( + fault = std::make_shared( "wfi in user mode or TW enabled", machInst); } @@ -1844,7 +1846,7 @@ decode QUADRANT default Unknown::unknown() { STATUS status = xc->readMiscReg(MISCREG_STATUS); auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) { - fault = make_shared( + fault = std::make_shared( "sfence in user mode or TVM enabled", machInst); } @@ -1852,7 +1854,7 @@ decode QUADRANT default Unknown::unknown() { }}, IsNonSpeculative, IsSerializeAfter, No_OpClass); 0x18: mret({{ if (xc->readMiscReg(MISCREG_PRV) != PRV_M) { - fault = make_shared( + fault = std::make_shared( "mret at lower privilege", machInst); NPC = NPC; } else { diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa index 389b5cf05..0f3329d4e 100644 --- a/src/arch/riscv/isa/formats/fp.isa +++ b/src/arch/riscv/isa/formats/fp.isa @@ -40,7 +40,7 @@ def template FloatExecute {{ STATUS status = xc->readMiscReg(MISCREG_STATUS); if (status.fs == FPUStatus::OFF) - fault = make_shared("FPU is off", machInst); + fault = std::make_shared("FPU is off", machInst); %(op_decl)s; %(op_rd)s; @@ -60,7 +60,8 @@ def template FloatExecute {{ break; case 0x4: // Round to nearest, ties to max magnitude not implemented - fault = make_shared(ROUND_MODE, machInst); + fault = std::make_shared( + ROUND_MODE, machInst); break; case 0x7: { uint8_t frm = xc->readMiscReg(MISCREG_FRM); @@ -79,7 +80,8 @@ def template FloatExecute {{ break; case 0x4: // Round to nearest, ties to max magnitude not implemented - fault = make_shared(ROUND_MODE, machInst); + fault = std::make_shared( + ROUND_MODE, machInst); break; default: fault = std::make_shared(frm, machInst); diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index b95af7623..a32326f8f 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -326,7 +326,7 @@ def template CSRExecute {{ if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) { std::string error = csprintf( "SATP access in user mode or with TVM enabled\n"); - fault = make_shared(error, machInst); + fault = std::make_shared(error, machInst); olddata = 0; } else { olddata = xc->readMiscReg(CSRData.at(csr).physIndex); @@ -338,7 +338,7 @@ def template CSRExecute {{ if (pm != PrivilegeMode::PRV_M) { std::string error = csprintf( "MSTATUS is only accessibly in machine mode\n"); - fault = make_shared(error, machInst); + fault = std::make_shared(error, machInst); olddata = 0; } else { olddata = xc->readMiscReg(CSRData.at(csr).physIndex); @@ -350,7 +350,7 @@ def template CSRExecute {{ olddata = xc->readMiscReg(CSRData.at(csr).physIndex); } else { std::string error = csprintf("Illegal CSR index %#x\n", csr); - fault = make_shared(error, machInst); + fault = std::make_shared(error, machInst); olddata = 0; } break; @@ -371,7 +371,8 @@ def template CSRExecute {{ if (bits(csr, 11, 10) == 0x3) { std::string error = csprintf("CSR %s is read-only\n", CSRData.at(csr).name); - fault = make_shared(error, machInst); + fault = std::make_shared( + error, machInst); } else { DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, CSRData.at(csr).name); @@ -390,8 +391,8 @@ def template CSRExecute {{ } else { std::string error = "Interrupt m bits are " "read-only\n"; - fault = make_shared(error, - machInst); + fault = std::make_shared( + error, machInst); } break; default: diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index 009f1434d..d77d68e44 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -70,7 +70,6 @@ output decoder {{ #include "sim/full_system.hh" using namespace RiscvISA; -using namespace std; }}; output exec {{ @@ -99,5 +98,4 @@ output exec {{ #include "sim/system.hh" using namespace RiscvISA; -using namespace std; }}; diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index 10c1378a5..6718b059a 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -54,7 +54,6 @@ #include "sim/syscall_return.hh" #include "sim/system.hh" -using namespace std; using namespace RiscvISA; RiscvProcess::RiscvProcess(const ProcessParams ¶ms, @@ -75,7 +74,7 @@ RiscvProcess64::RiscvProcess64(const ProcessParams ¶ms, const Addr next_thread_stack_base = stack_base - max_stack_size; const Addr brk_point = roundUp(image.maxAddr(), PageBytes); const Addr mmap_end = 0x4000000000000000L; - memState = make_shared(this, brk_point, stack_base, + memState = std::make_shared(this, brk_point, stack_base, max_stack_size, next_thread_stack_base, mmap_end); } @@ -88,7 +87,7 @@ RiscvProcess32::RiscvProcess32(const ProcessParams ¶ms, const Addr next_thread_stack_base = stack_base - max_stack_size; const Addr brk_point = roundUp(image.maxAddr(), PageBytes); const Addr mmap_end = 0x40000000L; - memState = make_shared(this, brk_point, stack_base, + memState = std::make_shared(this, brk_point, stack_base, max_stack_size, next_thread_stack_base, mmap_end); } @@ -129,13 +128,13 @@ RiscvProcess::argsInit(int pageSize) // Determine stack size and populate auxv Addr stack_top = memState->getStackMin(); stack_top -= RandomBytes; - for (const string& arg: argv) + for (const std::string& arg: argv) stack_top -= arg.size() + 1; - for (const string& env: envp) + for (const std::string& env: envp) stack_top -= env.size() + 1; stack_top &= -addrSize; - vector> auxv; + std::vector> auxv; if (elfObject != nullptr) { auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint()); auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount()); @@ -157,18 +156,18 @@ RiscvProcess::argsInit(int pageSize) // Copy random bytes (for AT_RANDOM) to stack memState->setStackMin(memState->getStackMin() - RandomBytes); uint8_t at_random[RandomBytes]; - generate(begin(at_random), end(at_random), - [&]{ return random_mt.random(0, 0xFF); }); + std::generate(std::begin(at_random), std::end(at_random), + [&]{ return random_mt.random(0, 0xFF); }); initVirtMem->writeBlob(memState->getStackMin(), at_random, RandomBytes); // Copy argv to stack - vector argPointers; - for (const string& arg: argv) { + std::vector argPointers; + for (const std::string& arg: argv) { memState->setStackMin(memState->getStackMin() - (arg.size() + 1)); initVirtMem->writeString(memState->getStackMin(), arg.c_str()); argPointers.push_back(memState->getStackMin()); if (DTRACE(Stack)) { - string wrote; + std::string wrote; initVirtMem->readString(wrote, argPointers.back()); DPRINTFN("Wrote arg \"%s\" to address %p\n", wrote, (void*)memState->getStackMin()); @@ -177,8 +176,8 @@ RiscvProcess::argsInit(int pageSize) argPointers.push_back(0); // Copy envp to stack - vector envPointers; - for (const string& env: envp) { + std::vector envPointers; + for (const std::string& env: envp) { memState->setStackMin(memState->getStackMin() - (env.size() + 1)); initVirtMem->writeString(memState->getStackMin(), env.c_str()); envPointers.push_back(memState->getStackMin()); @@ -222,7 +221,7 @@ RiscvProcess::argsInit(int pageSize) } // Push aux vector onto stack - std::map aux_keys = { + std::map aux_keys = { {M5_AT_ENTRY, "M5_AT_ENTRY"}, {M5_AT_PHNUM, "M5_AT_PHNUM"}, {M5_AT_PHENT, "M5_AT_PHENT"}, diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc index 75f1820e4..021b388a7 100644 --- a/src/arch/riscv/remote_gdb.cc +++ b/src/arch/riscv/remote_gdb.cc @@ -148,7 +148,6 @@ #include "mem/page_table.hh" #include "sim/full_system.hh" -using namespace std; using namespace RiscvISA; RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port) diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc index c1ed30e02..491f15feb 100644 --- a/src/arch/riscv/tlb.cc +++ b/src/arch/riscv/tlb.cc @@ -52,7 +52,6 @@ #include "sim/process.hh" #include "sim/system.hh" -using namespace std; using namespace RiscvISA; /////////////////////////////////////////////////////////////////////// @@ -359,7 +358,7 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc, code = ExceptionCode::STORE_ACCESS; else code = ExceptionCode::INST_ACCESS; - fault = make_shared(req->getVaddr(), code); + fault = std::make_shared(req->getVaddr(), code); } return fault; @@ -373,7 +372,7 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc, // the start. assert(req->getSize() > 0); if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) - return make_shared(req->getVaddr()); + return std::make_shared(req->getVaddr()); Process * p = tc->getProcessPtr(); -- 2.30.2