From e645bc6939794a95ecd7b0f5dbd9de07332ef365 Mon Sep 17 00:00:00 2001 From: Caio Marcelo de Oliveira Filho Date: Tue, 28 Apr 2020 13:28:02 -0700 Subject: [PATCH] intel: Let drivers call brw_nir_lower_cs_intrinsics() The motivating factor is: this lowering may cause nir_intrinsic_load_local_group_size intrinsics to be added to the shader, and by moving this around we make possible for the drivers to lower that intrinsic by themselves. Iris will do just that in a later patch for implementing variable group size. Reviewed-by: Kenneth Graunke Reviewed-by: Jordan Justen Part-of: --- src/gallium/drivers/iris/iris_program.c | 2 ++ src/intel/compiler/brw_fs.cpp | 2 -- src/intel/vulkan/anv_pipeline.c | 1 + src/mesa/drivers/dri/i965/brw_cs.c | 2 ++ 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index d1cee0df841..8cf15c6ced9 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -1947,6 +1947,8 @@ iris_compile_cs(struct iris_context *ice, nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir); + NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics); + iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values, &num_system_values, &num_cbufs); diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 8725b78a647..089fb15a48e 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -9006,8 +9006,6 @@ compile_cs_to_nir(const struct brw_compiler *compiler, nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true); - NIR_PASS_V(shader, brw_nir_lower_cs_intrinsics); - NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width); /* Clean up after the local index and ID calculations. */ diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 5c6150d26ff..0767aaf6cf2 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1660,6 +1660,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline, nir_var_mem_shared, shared_type_info); NIR_PASS_V(stage.nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset); + NIR_PASS_V(stage.nir, brw_nir_lower_cs_intrinsics); stage.num_stats = 1; stage.code = brw_compile_cs(compiler, pipeline->base.device, mem_ctx, diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c index 1f2fefc2fb3..d6aceccd9f0 100644 --- a/src/mesa/drivers/dri/i965/brw_cs.c +++ b/src/mesa/drivers/dri/i965/brw_cs.c @@ -118,6 +118,8 @@ brw_codegen_cs_prog(struct brw_context *brw, gl_ctx->Const.MaxComputeVariableGroupInvocations; } + brw_nir_lower_cs_intrinsics(nir); + char *error_str; program = brw_compile_cs(brw->screen->compiler, brw, mem_ctx, key, &prog_data, nir, st_index, NULL, &error_str); -- 2.30.2