From e64b9d5a4d40ff5a86f35a17ac81786a647726d3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 29 Sep 2017 17:52:57 +0200 Subject: [PATCH] Fix synth_ice40 doc regarding -top default --- techlibs/ice40/synth_ice40.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2533d3af8..a49372c8a 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -38,7 +38,7 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" use the specified module as top module\n"); log("\n"); log(" -blif \n"); log(" write the design to the specified BLIF file. writing of an output file\n"); -- 2.30.2