From e6536d4b8bf93cdb5456b6cd97cfbc4ebc41f34c Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 25 Sep 2019 20:03:46 +1000 Subject: [PATCH] divider: Always compute result/sresult/d_out.write_reg_data These are intended to be combinatorial. The previous code was giving warnings in vivado about registers/latches with no clock defined. Signed-off-by: Paul Mackerras --- divider.vhdl | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/divider.vhdl b/divider.vhdl index 6b20576..c133522 100644 --- a/divider.vhdl +++ b/divider.vhdl @@ -108,20 +108,21 @@ begin d_out <= DividerToWritebackInit; d_out.write_reg_nr <= write_reg; + if is_modulus = '1' then + result <= dend(127 downto 64); + else + result <= quot; + end if; + if neg_result = '1' then + sresult <= std_ulogic_vector(- signed(result)); + else + sresult <= result; + end if; + d_out.write_reg_data <= sresult; + if count(6) = '1' then d_out.valid <= '1'; d_out.write_reg_enable <= '1'; - if is_modulus = '1' then - result <= dend(127 downto 64); - else - result <= quot; - end if; - if neg_result = '1' then - sresult <= std_ulogic_vector(- signed(result)); - else - sresult <= result; - end if; - d_out.write_reg_data <= sresult; if rc = '1' then d_out.write_cr_enable <= '1'; d_out.write_cr_mask <= num_to_fxm(0); -- 2.30.2