From e667d5ae5330ec8381a7408a256d5557bd6dd6db Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Jun 2019 09:59:10 +0200 Subject: [PATCH] README: update Intro --- README | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/README b/README index be15f513..bcb49d87 100644 --- a/README +++ b/README @@ -9,11 +9,11 @@ [> Intro -------- -LiteX is a FPGA design/SoC builder that can be used to build cores, create -SoCs and full FPGA designs. +LiteX is a MiSoC-based SoC builder using Migen as Python DSL that can be used +to create SoCs and full FPGA designs. -LiteX is based on Migen and provides specific building/debugging tools for -a higher level of abstraction and compatibily with the LiteX core ecosystem. +LiteX provides specific building/debugging tools for high level of abstraction +and compatibily with the LiteX core ecosystem. Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a toolbox to create/develop/debug FPGA SoCs in Python. -- 2.30.2