From e689c00b16d40f52210cd185f668a351435c7af9 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 8 Apr 2014 13:26:29 -0500 Subject: [PATCH] ruby: coherence protocols: drop the phrase IntraChip The phrase is no longer valid since we do not distinguish between inter and intra chip communication. --- src/mem/protocol/MESI_Two_Level-L1cache.sm | 66 +++++++-------- src/mem/protocol/MESI_Two_Level-L2cache.sm | 98 +++++++++++----------- 2 files changed, 82 insertions(+), 82 deletions(-) diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index bd56b5660..49fd31207 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -259,8 +259,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") return tbe.pendingAcks; } - out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache); - out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache); + out_port(requestL1Network_out, RequestMsg, requestFromL1Cache); + out_port(responseL1Network_out, ResponseMsg, responseFromL1Cache); out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache); out_port(optionalQueue_out, RubyRequest, optionalQueue); @@ -346,10 +346,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } } - // Response IntraChip L1 Network - response msg to this L1 cache - in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) { - if (responseIntraChipL1Network_in.isReady()) { - peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") { + // Response L1 Network - response msg to this L1 cache + in_port(responseL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) { + if (responseL1Network_in.isReady()) { + peek(responseL1Network_in, ResponseMsg, block_on="Addr") { assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.Addr); @@ -387,9 +387,9 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } // Request InterChip network - request from this L1 cache to the shared L2 - in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank = 1) { - if(requestIntraChipL1Network_in.isReady()) { - peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") { + in_port(requestL1Network_in, RequestMsg, requestToL1Cache, rank = 1) { + if(requestL1Network_in.isReady()) { + peek(requestL1Network_in, RequestMsg, block_on="Addr") { assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.Addr); @@ -495,7 +495,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -512,7 +512,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; @@ -530,7 +530,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GET_INSTR; out_msg.Requestor := machineID; @@ -548,7 +548,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pai_issuePfGETINSTR, "pai", desc="Issue GETINSTR for prefetch request") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GET_INSTR; @@ -568,7 +568,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; @@ -586,7 +586,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") { peek(optionalQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, + enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; @@ -607,7 +607,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") action(c_issueUPGRADE, "c", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { - enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) { + enqueue(requestL1Network_out, RequestMsg, latency= l1_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:UPGRADE; out_msg.Requestor := machineID; @@ -623,8 +623,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d_sendDataToRequestor, "d", desc="send data to requestor") { - peek(requestIntraChipL1Network_in, RequestMsg) { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + peek(requestL1Network_in, RequestMsg) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -638,7 +638,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -652,8 +652,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") { - peek(requestIntraChipL1Network_in, RequestMsg) { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + peek(requestL1Network_in, RequestMsg) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -667,7 +667,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -681,8 +681,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") { - peek(requestIntraChipL1Network_in, RequestMsg) { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + peek(requestL1Network_in, RequestMsg) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -693,7 +693,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(f_sendDataToL2, "f", desc="send data to the L2 cache") { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -707,7 +707,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -721,8 +721,8 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(fi_sendInvAck, "fi", desc="send data to the L2 cache") { - peek(requestIntraChipL1Network_in, RequestMsg) { - enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) { + peek(requestL1Network_in, RequestMsg) { + enqueue(responseL1Network_out, ResponseMsg, latency=l1_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -741,7 +741,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(g_issuePUTX, "g", desc="send data to the L2 cache") { - enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) { + enqueue(requestL1Network_out, RequestMsg, latency=l1_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; @@ -837,11 +837,11 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") { - profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles()); + profileMsgDelay(2, requestL1Network_in.dequeue_getDelayCycles()); } action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") { - profileMsgDelay(1, responseIntraChipL1Network_in.dequeue_getDelayCycles()); + profileMsgDelay(1, responseL1Network_in.dequeue_getDelayCycles()); } action(s_deallocateTBE, "s", desc="Deallocate TBE") { @@ -850,7 +850,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(u_writeDataToL1Cache, "u", desc="Write data to cache") { - peek(responseIntraChipL1Network_in, ResponseMsg) { + peek(responseL1Network_in, ResponseMsg) { assert(is_valid(cache_entry)); cache_entry.DataBlk := in_msg.DataBlk; cache_entry.Dirty := in_msg.Dirty; @@ -858,7 +858,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } action(q_updateAckCount, "q", desc="Update ack count") { - peek(responseIntraChipL1Network_in, ResponseMsg) { + peek(responseL1Network_in, ResponseMsg) { assert(is_valid(tbe)); tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount; APPEND_TRANSITION_COMMENT(in_msg.AckCount); diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index 2b174bf76..5c240035a 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -265,9 +265,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") // ** OUT_PORTS ** - out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache); - out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache); - out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache); + out_port(L1RequestL2Network_out, RequestMsg, L1RequestFromL2Cache); + out_port(DirRequestL2Network_out, RequestMsg, DirRequestFromL2Cache); + out_port(responseL2Network_out, ResponseMsg, responseFromL2Cache); in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) { @@ -291,10 +291,10 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } - // Response IntraChip L2 Network - response msg to this particular L2 bank - in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) { - if (responseIntraChipL2Network_in.isReady()) { - peek(responseIntraChipL2Network_in, ResponseMsg) { + // Response L2 Network - response msg to this particular L2 bank + in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) { + if (responseL2Network_in.isReady()) { + peek(responseL2Network_in, ResponseMsg) { // test wether it's from a local L1 or an off chip source assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.Addr); @@ -333,9 +333,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } // L1 Request - in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) { - if(L1RequestIntraChipL2Network_in.isReady()) { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) { + if(L1RequestL2Network_in.isReady()) { + peek(L1RequestL2Network_in, RequestMsg) { Entry cache_entry := getCacheEntry(in_msg.Addr); TBE tbe := L2_TBEs[in_msg.Addr]; @@ -377,8 +377,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") // ACTIONS action(a_issueFetchToMemory, "a", desc="fetch data from memory") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(DirRequestL2Network_out, RequestMsg, latency=l2_request_latency) { out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; @@ -389,8 +389,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := in_msg.Type; @@ -402,7 +402,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(c_exclusiveReplacement, "c", desc="Send data to memory") { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; @@ -415,7 +415,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; @@ -425,7 +425,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { assert(is_valid(tbe)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; @@ -438,8 +438,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -457,8 +457,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -476,8 +476,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(responseL2Network_out, ResponseMsg, latency=l2_response_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -493,7 +493,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") { assert(is_valid(tbe)); assert(tbe.L1_GetS_IDs.count() > 0); - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; @@ -507,7 +507,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") { assert(is_valid(tbe)); assert(tbe.L1_GetS_IDs.count() == 1); - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; @@ -519,7 +519,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) { + enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { assert(is_valid(tbe)); assert(is_valid(cache_entry)); out_msg.Addr := address; @@ -535,7 +535,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") { - enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) { + enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -546,8 +546,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -559,8 +559,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(L1RequestL2Network_out, RequestMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceRequestType:INV; @@ -590,7 +590,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") { - profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles()); + profileMsgDelay(0, L1RequestL2Network_in.dequeue_getDelayCycles()); } action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") { @@ -598,11 +598,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") { - profileMsgDelay(1, responseIntraChipL2Network_in.dequeue_getDelayCycles()); + profileMsgDelay(1, responseL2Network_in.dequeue_getDelayCycles()); } action(m_writeDataToCache, "m", desc="Write data from response queue to cache") { - peek(responseIntraChipL2Network_in, ResponseMsg) { + peek(responseL2Network_in, ResponseMsg) { assert(is_valid(cache_entry)); cache_entry.DataBlk := in_msg.DataBlk; if (in_msg.Dirty) { @@ -612,7 +612,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(cache_entry)); cache_entry.DataBlk := in_msg.DataBlk; if (in_msg.Dirty) { @@ -622,7 +622,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(q_updateAck, "q", desc="update pending ack count") { - peek(responseIntraChipL2Network_in, ResponseMsg) { + peek(responseL2Network_in, ResponseMsg) { assert(is_valid(tbe)); tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount; APPEND_TRANSITION_COMMENT(in_msg.AckCount); @@ -632,7 +632,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") { - peek(responseIntraChipL2Network_in, ResponseMsg) { + peek(responseL2Network_in, ResponseMsg) { assert(is_valid(tbe)); tbe.DataBlk := in_msg.DataBlk; tbe.Dirty := in_msg.Dirty; @@ -640,14 +640,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(tbe)); tbe.L1_GetS_IDs.add(in_msg.Requestor); } } action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(tbe)); tbe.L1_GetX_ID := in_msg.Requestor; } @@ -669,8 +669,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(t_sendWBAck, "t", desc="Send writeback ACK") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { out_msg.Addr := address; out_msg.Type := CoherenceResponseType:WB_ACK; out_msg.Sender := machineID; @@ -681,8 +681,8 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { - enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) { + peek(L1RequestL2Network_in, RequestMsg) { + enqueue(responseL2Network_out, ResponseMsg, latency=to_l1_latency) { assert(is_valid(cache_entry)); out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; @@ -704,7 +704,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(nn_addSharer, "\n", desc="Add L1 sharer to list") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(cache_entry)); addSharer(address, in_msg.Requestor, cache_entry); APPEND_TRANSITION_COMMENT( cache_entry.Sharers ); @@ -719,21 +719,21 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(cache_entry)); cache_entry.Sharers.remove(in_msg.Requestor); } } action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(cache_entry)); cache_entry.Sharers.clear(); } } action(mm_markExclusive, "\m", desc="set the exclusive owner") { - peek(L1RequestIntraChipL2Network_in, RequestMsg) { + peek(L1RequestL2Network_in, RequestMsg) { assert(is_valid(cache_entry)); cache_entry.Sharers.clear(); cache_entry.Exclusive := in_msg.Requestor; @@ -751,11 +751,11 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") { - stall_and_wait(L1RequestIntraChipL2Network_in, address); + stall_and_wait(L1RequestL2Network_in, address); } action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") { - responseIntraChipL2Network_in.recycle(); + responseL2Network_in.recycle(); } action(kd_wakeUpDependents, "kd", desc="wake-up dependents") { -- 2.30.2