From e6901f35074301d3adad2efca048916073bae3a6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 17 Dec 2020 02:54:59 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index c18dfb27d..aae4c61f0 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -275,6 +275,9 @@ SV integer register `(5 << 2) + 0b01`, `SVCR6_011` is SV condition register `(6 << 3) + 0b011`, and `SVFR20_10` is SV floating-point register `(20 << 2) + 0b10`. +(Jacob i finally after several days, nearly a week, begin to vaguely understand this encoding. it is not at all the SV Prefix original one, which is what i W +was expecting to see. this encoding prevents and prohibits standard scalar v3.0B instructions from being able to interact. the encoding only allows access to a limited subset when scalar mode is set, and also violates the design goal of allowing "all zeros" to be the way to "switch off" SV) + ## Example Code a vectorized 32-bit add: -- 2.30.2