From e6ac6d3224f0d69e537daef93b42a1762b7af760 Mon Sep 17 00:00:00 2001 From: Dongwon Kim Date: Thu, 27 Jun 2019 09:54:33 -0700 Subject: [PATCH] intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11 correct bit fields information of CACHE_MODE_0 reg in current gen11.xml Signed-off-by: Dongwon Kim Reviewed-by: Anuj Phogat --- src/intel/genxml/gen11.xml | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 1579345f69f..c1774501f4c 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -6818,30 +6818,28 @@ - + - + - - - - - - + + + - + - - + + - + - - + + + - + - + -- 2.30.2