From e6ad0b153ec26de5529e6f28497b442833bc041d Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Wed, 21 Jan 2015 10:13:47 +0000 Subject: [PATCH] [ARM/AArch64][testsuite] Add vqdmlal_lane and vqdmlsl_lane tests. 2015-01-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file. From-SVN: r219931 --- gcc/testsuite/ChangeLog | 6 ++ .../advsimd-intrinsics/vqdmlXl_lane.inc | 73 +++++++++++++++++++ .../aarch64/advsimd-intrinsics/vqdmlal_lane.c | 38 ++++++++++ .../aarch64/advsimd-intrinsics/vqdmlsl_lane.c | 40 ++++++++++ 4 files changed, 157 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6414a125e62..23063a28b36 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2015-01-21 Christophe Lyon + + * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c: New file. + * gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c: New file. + 2015-01-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vqdmlXl.inc: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc new file mode 100644 index 00000000000..705f90ac5e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlXl_lane.inc @@ -0,0 +1,73 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* vector_res = vqdmlXl_lane(vector, vector3, vector4, lane), + then store the result. */ +#define TEST_VQDMLXL_LANE1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + Set_Neon_Cumulative_Sat(0, VECT_VAR(vector_res, T1, W, N)); \ + VECT_VAR(vector_res, T1, W, N) = \ + INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector3, T1, W2, N), \ + VECT_VAR(vector4, T1, W2, N), \ + V); \ + vst1q_##T2##W(VECT_VAR(result, T1, W, N), \ + VECT_VAR(vector_res, T1, W, N)); \ + CHECK_CUMULATIVE_SAT(TEST_MSG, T1, W, N, EXPECTED_CUMULATIVE_SAT, CMT) + +#define TEST_VQDMLXL_LANE(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) \ + TEST_VQDMLXL_LANE1(INSN, T1, T2, W, W2, N, V, EXPECTED_CUMULATIVE_SAT, CMT) + + DECL_VARIABLE(vector, int, 32, 4); + DECL_VARIABLE(vector3, int, 16, 4); + DECL_VARIABLE(vector4, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 4); + + DECL_VARIABLE(vector, int, 64, 2); + DECL_VARIABLE(vector3, int, 32, 2); + DECL_VARIABLE(vector4, int, 32, 2); + DECL_VARIABLE(vector_res, int, 64, 2); + + clean_results (); + + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, int, s, 64, 2); + + VDUP(vector3, , int, s, 16, 4, 0x55); + VDUP(vector4, , int, s, 16, 4, 0xBB); + VDUP(vector3, , int, s, 32, 2, 0x55); + VDUP(vector4, , int, s, 32, 2, 0xBB); + + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat, ""); + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat, ""); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + +#define TEST_MSG2 "(mul with input=0)" + VDUP(vector3, , int, s, 16, 4, 0); + VDUP(vector3, , int, s, 32, 2, 0); + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat2, TEST_MSG2); + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat2, TEST_MSG2); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected2, TEST_MSG2); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected2, TEST_MSG2); + +#define TEST_MSG3 "(mul with saturation)" + VDUP(vector3, , int, s, 16, 4, 0x8000); + VDUP(vector3, , int, s, 32, 2, 0x80000000); + VDUP(vector4, , int, s, 16, 4, 0x8000); + VDUP(vector4, , int, s, 32, 2, 0x80000000); + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 32, 16, 4, 0, expected_cumulative_sat3, TEST_MSG3); + TEST_VQDMLXL_LANE(INSN_NAME, int, s, 64, 32, 2, 0, expected_cumulative_sat3, TEST_MSG3); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected3, TEST_MSG3); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected3, TEST_MSG3); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c new file mode 100644 index 00000000000..832a7057558 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlal_lane.c @@ -0,0 +1,38 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlal_lane +#define TEST_MSG "VQDMLAL_LANE" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0x7c1e, 0x7c1f, 0x7c20, 0x7c21 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0x7c1e, 0x7c1f }; + +/* Expected values of cumulative_saturation flag when multiplying with + 0. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 0; + +/* Expected values when multiplying with 0. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff0, 0xfffffff1, + 0xfffffff2, 0xfffffff3 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; + +/* Expected values of cumulative_saturation flag when multiplication + saturates. */ +int VECT_VAR(expected_cumulative_sat3,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat3,int,64,2) = 1; + +/* Expected values when multiplication saturates. */ +VECT_VAR_DECL(expected3,int,32,4) [] = { 0x7fffffef, 0x7ffffff0, + 0x7ffffff1, 0x7ffffff2 }; +VECT_VAR_DECL(expected3,int,64,2) [] = { 0x7fffffffffffffef, + 0x7ffffffffffffff0 }; + +#include "vqdmlXl_lane.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c new file mode 100644 index 00000000000..b95e61c2b01 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqdmlsl_lane.c @@ -0,0 +1,40 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vqdmlsl_lane +#define TEST_MSG "VQDMLSL_LANE" + +/* Expected values of cumulative_saturation flag. */ +int VECT_VAR(expected_cumulative_sat,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat,int,64,2) = 0; + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0xffff83c2, 0xffff83c3, + 0xffff83c4, 0xffff83c5 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xffffffffffff83c2, + 0xffffffffffff83c3 }; + +/* Expected values of cumulative_saturation flag when multiplying with + 0. */ +int VECT_VAR(expected_cumulative_sat2,int,32,4) = 0; +int VECT_VAR(expected_cumulative_sat2,int,64,2) = 0; + +/* Expected values when multiplying with 0. */ +VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff0, 0xfffffff1, + 0xfffffff2, 0xfffffff3 }; +VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; + +/* Expected values of cumulative_saturation flag when multiplication + saturates. */ +int VECT_VAR(expected_cumulative_sat3,int,32,4) = 1; +int VECT_VAR(expected_cumulative_sat3,int,64,2) = 1; + +/* Expected values when multiplication saturates. */ +VECT_VAR_DECL(expected3,int,32,4) [] = { 0x80000000, 0x80000000, + 0x80000000, 0x80000000 }; +VECT_VAR_DECL(expected3,int,64,2) [] = { 0x8000000000000000, + 0x8000000000000000 }; + +#include "vqdmlXl_lane.inc" -- 2.30.2