From e6bbdd2822bcd8ad661a89b6502e8cfa90915f8a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 20 Sep 2022 10:56:56 +0100 Subject: [PATCH] add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible --- src/openpower/sv/trans/test_pysvp64dis.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 981147e1..98173ba5 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -256,6 +256,8 @@ class SVSTATETestCase(unittest.TestCase): self._do_tst(expected) def test_16_bc(self): + # hilarious. this should be autogenerated from a sequence + # of lists of options. it's a lot of frickin options. expected = [ "sv.bc/all 12,*1,0xc", "sv.bc/snz 12,*1,0xc", @@ -267,6 +269,7 @@ class SVSTATETestCase(unittest.TestCase): "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc", "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc", "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc", + "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc", ] self._do_tst(expected) -- 2.30.2