From e6bfe1c7734cfbf41a763797527db6cb49fa1566 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Tue, 19 Jul 2016 12:08:42 -0400 Subject: [PATCH] freedreno: move needs_wfi into batch This is also used in gmem code, which executes from the "bottom half" (ie. from the flush_queue worker thread), so it cannot be in fd_context. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/a3xx/fd3_draw.c | 6 ++-- src/gallium/drivers/freedreno/a3xx/fd3_emit.c | 14 ++++---- src/gallium/drivers/freedreno/a3xx/fd3_emit.h | 4 +-- src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 34 +++++++++---------- .../drivers/freedreno/a3xx/fd3_query.c | 2 +- src/gallium/drivers/freedreno/a4xx/fd4_draw.c | 6 ++-- src/gallium/drivers/freedreno/a4xx/fd4_draw.h | 2 +- src/gallium/drivers/freedreno/a4xx/fd4_emit.c | 2 +- src/gallium/drivers/freedreno/a4xx/fd4_gmem.c | 16 ++++----- .../drivers/freedreno/a4xx/fd4_query.c | 6 ++-- .../drivers/freedreno/freedreno_batch.c | 2 ++ .../drivers/freedreno/freedreno_batch.h | 34 +++++++++++++++++++ .../drivers/freedreno/freedreno_context.c | 2 -- .../drivers/freedreno/freedreno_context.h | 34 ------------------- .../drivers/freedreno/freedreno_draw.h | 2 +- .../drivers/freedreno/freedreno_gmem.c | 8 ++--- .../drivers/freedreno/freedreno_query_hw.c | 2 +- .../drivers/freedreno/freedreno_state.c | 1 + .../drivers/freedreno/ir3/ir3_shader.c | 10 +++--- 19 files changed, 93 insertions(+), 94 deletions(-) diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c index 34d782b95ce..44ae1f9db8a 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c @@ -237,7 +237,7 @@ fd3_clear_binning(struct fd_context *ctx, unsigned dirty) OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1); OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */ - fd_event_write(ctx, ring, PERFCOUNTER_STOP); + fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP); fd_draw(ctx->batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY, DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL); @@ -285,7 +285,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers, A3XX_RB_DEPTH_CONTROL_Z_ENABLE | A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)); - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_ZOFFSET, 2); OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0)); OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(depth)); @@ -371,7 +371,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers, OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1); OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */ - fd_event_write(ctx, ring, PERFCOUNTER_STOP); + fd_event_write(ctx->batch, ring, PERFCOUNTER_STOP); fd_draw(ctx->batch, ring, DI_PT_RECTLIST, USE_VISIBILITY, DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL); diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index 7e83157e38e..0aef89f4054 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -586,7 +586,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, int i = ffs(planes) - 1; planes &= ~(1U << i); - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4); OUT_RING(ring, fui(ctx->ucp.ucp[i][0])); OUT_RING(ring, fui(ctx->ucp.ucp[i][1])); @@ -638,7 +638,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, } if (dirty & FD_DIRTY_VIEWPORT) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5)); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0])); @@ -734,7 +734,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, } if (dirty & (FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX)) - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); if (dirty & FD_DIRTY_VERTTEX) { if (vp->has_samp) @@ -770,7 +770,7 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_RING(ring, 0x00000000); } - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); OUT_RING(ring, 0x00007fff); @@ -840,7 +840,7 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) | A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0)); - fd3_emit_cache_flush(ctx, ring); + fd3_emit_cache_flush(batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1); OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */ @@ -877,7 +877,7 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1); OUT_RING(ring, 0x00000000); - fd_event_write(ctx, ring, CACHE_FLUSH); + fd_event_write(batch, ring, CACHE_FLUSH); if (is_a3xx_p0(ctx->screen)) { OUT_PKT3(ring, CP_DRAW_INDX, 3); @@ -893,7 +893,7 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); fd_hw_query_enable(batch, ring); diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h index dfe77589542..d8e5991cab9 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.h +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.h @@ -98,9 +98,9 @@ void fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring); void fd3_emit_init(struct pipe_context *pctx); static inline void -fd3_emit_cache_flush(struct fd_context *ctx, struct fd_ringbuffer *ring) +fd3_emit_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring) { - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2); OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0)); OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) | diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c index 1788c0c7384..34e0e39aad7 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c @@ -257,7 +257,7 @@ emit_binning_workaround(struct fd_batch *batch) OUT_RING(ring, A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(31) | A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(0)); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0)); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0)); @@ -284,7 +284,7 @@ emit_binning_workaround(struct fd_batch *batch) OUT_RING(ring, 2); /* NumIndices */ OUT_RING(ring, 2); OUT_RING(ring, 1); - fd_reset_wfi(ctx); + fd_reset_wfi(batch); OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 1); OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS)); @@ -292,7 +292,7 @@ emit_binning_workaround(struct fd_batch *batch) OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1); OUT_RING(ring, 0x00000000); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); OUT_RING(ring, A3XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) | A3XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h)); @@ -393,7 +393,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1); OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */ - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width/2.0 - 0.5)); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width/2.0)); @@ -565,7 +565,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile) OUT_RING(ring, fui(x1)); OUT_RING(ring, fui(y1)); - fd3_emit_cache_flush(ctx, ring); + fd3_emit_cache_flush(batch, ring); for (i = 0; i < 4; i++) { OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1); @@ -586,7 +586,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile) OUT_RING(ring, A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS) | A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w)); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1); OUT_RING(ring, A3XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS)); @@ -597,7 +597,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile) OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1); OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER); /* GRAS_CL_CLIP_CNTL */ - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w/2.0 - 0.5)); OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w/2.0)); @@ -808,7 +808,7 @@ emit_binning_pass(struct fd_batch *batch) if (ctx->screen->gpu_id == 320) { emit_binning_workaround(batch); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT3(ring, CP_INVALIDATE_STATE, 1); OUT_RING(ring, 0x00007fff); } @@ -862,9 +862,9 @@ emit_binning_pass(struct fd_batch *batch) /* emit IB to binning drawcmds: */ ctx->emit_ib(ring, batch->binning); - fd_reset_wfi(ctx); + fd_reset_wfi(batch); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); /* and then put stuff back the way it was: */ @@ -893,8 +893,8 @@ emit_binning_pass(struct fd_batch *batch) A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) | A3XX_RB_RENDER_CONTROL_BIN_WIDTH(gmem->bin_w)); - fd_event_write(ctx, ring, CACHE_FLUSH); - fd_wfi(ctx, ring); + fd_event_write(batch, ring, CACHE_FLUSH); + fd_wfi(batch, ring); if (ctx->screen->gpu_id == 320) { /* dummy-draw workaround: */ @@ -903,7 +903,7 @@ emit_binning_pass(struct fd_batch *batch) OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0)); OUT_RING(ring, 0); /* NumIndices */ - fd_reset_wfi(ctx); + fd_reset_wfi(batch); } OUT_PKT3(ring, CP_NOP, 4); @@ -912,7 +912,7 @@ emit_binning_pass(struct fd_batch *batch) OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); if (ctx->screen->gpu_id == 320) { emit_binning_workaround(batch); @@ -962,7 +962,7 @@ fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) struct pipe_framebuffer_state *pfb = &batch->framebuffer; if (ctx->needs_rb_fbd) { - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_RB_FRAME_BUFFER_DIMENSION, 1); OUT_RING(ring, A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) | A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height)); @@ -1015,8 +1015,8 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile) assert(pipe->w * pipe->h); - fd_event_write(ctx, ring, HLSQ_FLUSH); - fd_wfi(ctx, ring); + fd_event_write(batch, ring, HLSQ_FLUSH); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1); OUT_RING(ring, A3XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) | diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_query.c b/src/gallium/drivers/freedreno/a3xx/fd3_query.c index ec034fc127d..cce165c0410 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_query.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_query.c @@ -68,7 +68,7 @@ occlusion_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring) INDEX_SIZE_IGN, USE_VISIBILITY, 0)); OUT_RING(ring, 0); /* NumIndices */ - fd_event_write(batch->ctx, ring, ZPASS_DONE); + fd_event_write(batch, ring, ZPASS_DONE); OUT_PKT0(ring, REG_A3XX_RBBM_PERFCTR_CTL, 1); OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE); diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c index 8270c4f0cff..f217619848a 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c @@ -166,7 +166,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) struct fd_ringbuffer *ring = ctx->batch->draw; if (ctx->rasterizer->rasterizer_discard) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT3(ring, CP_REG_RMW, 3); OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL); OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE); @@ -176,7 +176,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) draw_impl(ctx, ctx->batch->draw, &emit); if (ctx->rasterizer->rasterizer_discard) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT3(ring, CP_REG_RMW, 3); OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL); OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE); @@ -285,7 +285,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, A4XX_RB_DEPTH_CONTROL_Z_ENABLE | A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS)); - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2); OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0)); OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth)); diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h index 57b16870fab..09d07bb9799 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.h +++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.h @@ -84,7 +84,7 @@ fd4_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, emit_marker(ring, 7); - fd_reset_wfi(batch->ctx); + fd_reset_wfi(batch); } diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c index 9ce93f6e33f..7ddb38a588b 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c @@ -632,7 +632,7 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, } if (dirty & FD_DIRTY_VIEWPORT) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6); OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0])); OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0])); diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c index 3f3847c2a28..d9b0631306d 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c @@ -228,7 +228,7 @@ fd4_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile) OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1); OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0)); - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1); OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */ @@ -641,8 +641,8 @@ emit_binning_pass(struct fd_batch *batch) /* emit IB to binning drawcmds: */ ctx->emit_ib(ring, batch->binning); - fd_reset_wfi(ctx); - fd_wfi(ctx, ring); + fd_reset_wfi(batch); + fd_wfi(batch, ring); /* and then put stuff back the way it was: */ @@ -655,8 +655,8 @@ emit_binning_pass(struct fd_batch *batch) A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) | A4XX_GRAS_SC_CONTROL_RASTER_MODE(0)); - fd_event_write(ctx, ring, CACHE_FLUSH); - fd_wfi(ctx, ring); + fd_event_write(batch, ring, CACHE_FLUSH); + fd_wfi(batch, ring); } /* before first tile */ @@ -746,7 +746,7 @@ fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile) } if (ctx->needs_rb_fbd) { - fd_wfi(ctx, ring); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1); OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) | A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height)); @@ -774,8 +774,8 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile) assert(pipe->w * pipe->h); - fd_event_write(ctx, ring, HLSQ_FLUSH); - fd_wfi(ctx, ring); + fd_event_write(batch, ring, HLSQ_FLUSH); + fd_wfi(batch, ring); OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1); OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) | diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_query.c b/src/gallium/drivers/freedreno/a4xx/fd4_query.c index 921384c1911..3ae3971dc5f 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_query.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_query.c @@ -73,7 +73,7 @@ occlusion_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_RING(ring, 1); /* NumInstances */ OUT_RING(ring, 0); /* NumIndices */ - fd_event_write(batch->ctx, ring, ZPASS_DONE); + fd_event_write(batch, ring, ZPASS_DONE); return samp; } @@ -117,7 +117,7 @@ time_elapsed_enable(struct fd_context *ctx, struct fd_ringbuffer *ring) * just hard coded. If we start exposing more countables than we * have counters, we will need to be more clever. */ - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); OUT_PKT0(ring, REG_A4XX_CP_PERFCTR_CP_SEL_0, 1); OUT_RING(ring, CP_ALWAYS_COUNT); } @@ -161,7 +161,7 @@ time_elapsed_get_sample(struct fd_batch *batch, struct fd_ringbuffer *ring) * shot, but that's really just polishing a turd.. */ - fd_wfi(batch->ctx, ring); + fd_wfi(batch, ring); /* copy sample counter _LO and _HI to scratch: */ OUT_PKT3(ring, CP_REG_TO_MEM, 2); diff --git a/src/gallium/drivers/freedreno/freedreno_batch.c b/src/gallium/drivers/freedreno/freedreno_batch.c index 219e0a80988..088ae2df635 100644 --- a/src/gallium/drivers/freedreno/freedreno_batch.c +++ b/src/gallium/drivers/freedreno/freedreno_batch.c @@ -67,6 +67,8 @@ batch_init(struct fd_batch *batch) batch->num_draws = 0; batch->stage = FD_STAGE_NULL; + fd_reset_wfi(batch); + /* reset maximal bounds: */ batch->max_scissor.minx = batch->max_scissor.miny = ~0; batch->max_scissor.maxx = batch->max_scissor.maxy = 0; diff --git a/src/gallium/drivers/freedreno/freedreno_batch.h b/src/gallium/drivers/freedreno/freedreno_batch.h index 9b7a8c132b1..1d27a8f0234 100644 --- a/src/gallium/drivers/freedreno/freedreno_batch.h +++ b/src/gallium/drivers/freedreno/freedreno_batch.h @@ -93,6 +93,11 @@ struct fd_batch { bool blit : 1; bool back_blit : 1; /* only blit so far is resource shadowing back-blit */ + /* Keep track if WAIT_FOR_IDLE is needed for registers we need + * to update via RMW: + */ + bool needs_wfi : 1; + /* To decide whether to render to system memory, keep track of the * number of draws, and whether any of them require multisample, * depth_test (or depth write), stencil_test, blending, and @@ -212,4 +217,33 @@ fd_batch_reference(struct fd_batch **ptr, struct fd_batch *batch) *ptr = batch; } +static inline void +fd_reset_wfi(struct fd_batch *batch) +{ + batch->needs_wfi = true; +} + +/* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already + * been one since last draw: + */ +static inline void +fd_wfi(struct fd_batch *batch, struct fd_ringbuffer *ring) +{ + if (batch->needs_wfi) { + OUT_WFI(ring); + batch->needs_wfi = false; + } +} + +/* emit a CP_EVENT_WRITE: + */ +static inline void +fd_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring, + enum vgt_event_type evt) +{ + OUT_PKT3(ring, CP_EVENT_WRITE, 1); + OUT_RING(ring, evt); + fd_reset_wfi(batch); +} + #endif /* FREEDRENO_BATCH_H_ */ diff --git a/src/gallium/drivers/freedreno/freedreno_context.c b/src/gallium/drivers/freedreno/freedreno_context.c index 599f94ffec1..269602e1496 100644 --- a/src/gallium/drivers/freedreno/freedreno_context.c +++ b/src/gallium/drivers/freedreno/freedreno_context.c @@ -188,8 +188,6 @@ fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen, util_queue_init(&ctx->flush_queue, "flush_queue", 16, 1); } - fd_reset_wfi(ctx); - util_slab_create(&ctx->transfer_pool, sizeof(struct fd_transfer), 16, UTIL_SLAB_SINGLETHREADED); diff --git a/src/gallium/drivers/freedreno/freedreno_context.h b/src/gallium/drivers/freedreno/freedreno_context.h index 2d88cdcbd8c..557e3715b3b 100644 --- a/src/gallium/drivers/freedreno/freedreno_context.h +++ b/src/gallium/drivers/freedreno/freedreno_context.h @@ -176,11 +176,6 @@ struct fd_context { */ bool in_blit : 1; - /* Keep track if WAIT_FOR_IDLE is needed for registers we need - * to update via RMW: - */ - bool needs_wfi : 1; - /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION? At least on a3xx * it is not a banked context register, so it needs a WFI to update. * Keep track if it has actually changed, to avoid unneeded WFI. @@ -308,35 +303,6 @@ fd_supported_prim(struct fd_context *ctx, unsigned prim) return (1 << prim) & ctx->primtype_mask; } -static inline void -fd_reset_wfi(struct fd_context *ctx) -{ - ctx->needs_wfi = true; -} - -/* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already - * been one since last draw: - */ -static inline void -fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring) -{ - if (ctx->needs_wfi) { - OUT_WFI(ring); - ctx->needs_wfi = false; - } -} - -/* emit a CP_EVENT_WRITE: - */ -static inline void -fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring, - enum vgt_event_type evt) -{ - OUT_PKT3(ring, CP_EVENT_WRITE, 1); - OUT_RING(ring, evt); - fd_reset_wfi(ctx); -} - struct pipe_context * fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen, const uint8_t *primtypes, void *priv); diff --git a/src/gallium/drivers/freedreno/freedreno_draw.h b/src/gallium/drivers/freedreno/freedreno_draw.h index 60cd9c09881..18a50379ef3 100644 --- a/src/gallium/drivers/freedreno/freedreno_draw.h +++ b/src/gallium/drivers/freedreno/freedreno_draw.h @@ -93,7 +93,7 @@ fd_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, emit_marker(ring, 7); - fd_reset_wfi(batch->ctx); + fd_reset_wfi(batch); } diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c index f2b6792fde7..ed625e455af 100644 --- a/src/gallium/drivers/freedreno/freedreno_gmem.c +++ b/src/gallium/drivers/freedreno/freedreno_gmem.c @@ -332,7 +332,7 @@ render_tiles(struct fd_batch *batch) /* emit IB to drawcmds: */ ctx->emit_ib(batch->gmem, batch->draw); - fd_reset_wfi(ctx); + fd_reset_wfi(batch); /* emit gmem2mem to transfer tile back to system memory: */ ctx->emit_tile_gmem2mem(batch, tile); @@ -350,7 +350,7 @@ render_sysmem(struct fd_batch *batch) /* emit IB to drawcmds: */ ctx->emit_ib(batch->gmem, batch->draw); - fd_reset_wfi(ctx); + fd_reset_wfi(batch); } void @@ -369,7 +369,7 @@ fd_gmem_render_tiles(struct fd_batch *batch) } } - fd_reset_wfi(ctx); + fd_reset_wfi(batch); ctx->stats.batch_total++; @@ -394,8 +394,6 @@ fd_gmem_render_tiles(struct fd_batch *batch) } fd_ringbuffer_flush(batch->gmem); - - fd_reset_wfi(ctx); } /* tile needs restore if it isn't completely contained within the diff --git a/src/gallium/drivers/freedreno/freedreno_query_hw.c b/src/gallium/drivers/freedreno/freedreno_query_hw.c index b61ea0d5e08..481c66d3925 100644 --- a/src/gallium/drivers/freedreno/freedreno_query_hw.c +++ b/src/gallium/drivers/freedreno/freedreno_query_hw.c @@ -399,7 +399,7 @@ fd_hw_query_prepare_tile(struct fd_batch *batch, uint32_t n, if (tile_stride == 0) return; - fd_wfi(batch->ctx, ring); + fd_wfi(batch, ring); OUT_PKT0 (ring, HW_QUERY_BASE_REG, 1); OUT_RELOCW(ring, fd_resource(batch->query_buf)->bo, offset, 0, 0); } diff --git a/src/gallium/drivers/freedreno/freedreno_state.c b/src/gallium/drivers/freedreno/freedreno_state.c index c7d83692741..6dad07515a1 100644 --- a/src/gallium/drivers/freedreno/freedreno_state.c +++ b/src/gallium/drivers/freedreno/freedreno_state.c @@ -128,6 +128,7 @@ fd_set_framebuffer_state(struct pipe_context *pctx, batch = fd_batch_from_fb(&ctx->screen->batch_cache, ctx, framebuffer); fd_batch_reference(&ctx->batch, NULL); + fd_reset_wfi(batch); ctx->batch = batch; ctx->dirty = ~0; diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c index 5d57c0b69fa..501382fb71e 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c @@ -508,7 +508,7 @@ emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v, size = MIN2(size, 4 * max_const); if (size > 0) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); ctx->emit_const(ring, v->type, 0, cb->buffer_offset, size, cb->user_buffer, cb->buffer); @@ -541,7 +541,7 @@ emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v, } } - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets); } } @@ -563,7 +563,7 @@ emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v, size *= 4; if (size > 0) { - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); ctx->emit_const(ring, v->type, base, 0, size, v->immediates[0].val, NULL); } @@ -596,7 +596,7 @@ emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v, } } - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets); } } @@ -698,7 +698,7 @@ ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring, vertex_params_size = ARRAY_SIZE(vertex_params); } - fd_wfi(ctx, ring); + fd_wfi(ctx->batch, ring); ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0, vertex_params_size, vertex_params, NULL); -- 2.30.2