From e6ec500e19f455237828f4f3955f888ad0b56382 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 20 Aug 2010 15:32:17 -0700 Subject: [PATCH] i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB. --- src/mesa/drivers/dri/i965/brw_eu.h | 1 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 13 +++++++------ src/mesa/drivers/dri/i965/brw_wm_emit.c | 21 ++++++++++----------- 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 1ead4455d3a..6e9e210cf17 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -845,6 +845,7 @@ void brw_ff_sync(struct brw_compile *p, GLboolean eot); void brw_fb_WRITE(struct brw_compile *p, + int dispatch_width, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index c9b4770fd9a..a6ca030afe5 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1350,6 +1350,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p, void brw_fb_WRITE(struct brw_compile *p, + int dispatch_width, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, @@ -1370,18 +1371,18 @@ void brw_fb_WRITE(struct brw_compile *p, /* headerless version, just submit color payload */ src0 = brw_message_reg(msg_reg_nr); - if (msg_length >= 8) - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; - else - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6; } else { insn->header.destreg__conditionalmod = msg_reg_nr; - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; - msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; + msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; } + if (dispatch_width == 16) + msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; + else + msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; + brw_set_dest(insn, dest); brw_set_src0(insn, src0); brw_set_dp_write_message(p->brw, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 78de2ceda95..5c07108eb82 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1255,6 +1255,7 @@ static void fire_fb_write( struct brw_wm_compile *c, /* Send framebuffer write message: */ /* send (16) null.0<1>:uw m0 r0.0<8;8,1>:uw 0x85a04000:ud { Align1 EOT } */ brw_fb_WRITE(p, + c->dispatch_width, dst, base_reg, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), @@ -1376,17 +1377,10 @@ void emit_fb_write(struct brw_wm_compile *c, } /* skip over the regs populated above: */ - if (intel->gen < 6) { - nr += 8; /* XXX: always uses SIMD16 write currently. */ - } else { - if (c->dispatch_width == 16) - nr += 8; - else - nr += 4; - - /* Subtract off the message header, since we send headerless. */ - nr -= 2; - } + if (c->dispatch_width == 16) + nr += 8; + else + nr += 4; brw_pop_insn_state(p); @@ -1420,6 +1414,11 @@ void emit_fb_write(struct brw_wm_compile *c, nr += 2; } + if (intel->gen >= 6) { + /* Subtract off the message header, since we send headerless. */ + nr -= 2; + } + if (!c->key.runtime_check_aads_emit) { if (c->key.aa_dest_stencil_reg) emit_aa(c, arg1, 2); -- 2.30.2