From e709fd3da1c7e3ae36ee43a997fbd413909c764e Mon Sep 17 00:00:00 2001
From: Alyssa Milburn <amilburn@zall.org>
Date: Sun, 15 Dec 2019 20:40:38 +0100
Subject: [PATCH] Fix opt_expr.eqneq.cmpzero debug print

---
 passes/opt/opt_expr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 6cf66fb95..4a2f170b8 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -978,7 +978,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		{
 			cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
 			log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
-					log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
+					log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool");
 			cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
 			if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
 				cell->setPort(ID::A, cell->getPort(ID::B));
-- 
2.30.2