From e726ad80ac8eec85ba1d1f35c6a0de716ce469ef Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Jul 2019 19:01:55 +0200 Subject: [PATCH] cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) --- litex/soc/cores/spi_flash.py | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index 65e32cd4..caf81b80 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -12,8 +12,10 @@ from migen.genlib.misc import timeline from litex.gen import * from litex.soc.interconnect import wishbone -from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus +from litex.soc.interconnect.csr import * +from litex.soc.cores.spi import SPIMaster +# SpiFlash Quad/Dual/Single (memory-mapped) -------------------------------------------------------- _FAST_READ = 0x0b _DIOFR = 0xbb @@ -275,3 +277,31 @@ def SpiFlash(pads, *args, **kw): return SpiFlashSingle(pads, *args, **kw) else: return SpiFlashDualQuad(pads, *args, **kw) + + +# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ---------------------------------------------- + +class S7SPIFlash(Module, AutoCSR): + def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6): + self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) + self.specials += Instance("STARTUPE2", + i_CLK=0, + i_GSR=0, + i_GTS=0, + i_KEYCLEARB=0, + i_PACK=0, + i_USRCCLKO=spi.pads.clk, + i_USRCCLKTS=0, + i_USRDONEO=1, + i_USRDONETS=1 + ) + if hasattr(pads, "vpp"): + pads.vpp.reset = 1 + if hasattr(pads, "hold"): + pads.hold.reset = 1 + + self.comb += [ + pads.cs_n.eq(spi.pads.cs_n), + pads.mosi.eq(spi.pads.mosi), + spi.pads.miso.eq(pads.miso) + ] -- 2.30.2