From e729504fb1799c3ae31cea76d73946530ef9806f Mon Sep 17 00:00:00 2001 From: Timothy Arceri Date: Thu, 15 Sep 2016 12:20:38 +1000 Subject: [PATCH] nir: pass compiler rather than devinfo to functions that call nir_optimize Later we will pass compiler to nir_optimise to be used by the loop unroll pass. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 ++++------ src/mesa/drivers/dri/i965/brw_nir.c | 7 ++++--- src/mesa/drivers/dri/i965/brw_nir.h | 4 ++-- src/mesa/drivers/dri/i965/brw_shader.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 ++--- src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 5 ++--- src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 4 ++-- 7 files changed, 18 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 671b44bd50d..c8a069386dd 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -6396,14 +6396,13 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, char **error_str) { nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); - shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex, - true); + shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true); brw_nir_lower_fs_inputs(shader, vue_map, prog, compiler->devinfo, key); brw_nir_lower_fs_outputs(shader); if (!key->multisample_fbo) NIR_PASS_V(shader, demote_sample_qualifiers); NIR_PASS_V(shader, move_interpolation_to_top); - shader = brw_postprocess_nir(shader, compiler->devinfo, true); + shader = brw_postprocess_nir(shader, compiler, true); /* key->alpha_test_func means simulating alpha testing via discards, * so the shader definitely kills pixels. @@ -6628,8 +6627,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, char **error_str) { nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); - shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex, - true); + shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true); brw_nir_lower_cs_shared(shader); prog_data->base.total_shared += shader->num_shared; @@ -6642,7 +6640,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data, (unsigned)4 * (prog_data->thread_local_id_index + 1)); brw_nir_lower_intrinsics(shader, &prog_data->base); - shader = brw_postprocess_nir(shader, compiler->devinfo, true); + shader = brw_postprocess_nir(shader, compiler, true); prog_data->local_size[0] = shader->info->cs.local_size[0]; prog_data->local_size[1] = shader->info->cs.local_size[1]; diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c index 2697bb07c37..9a217ad4d12 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.c +++ b/src/mesa/drivers/dri/i965/brw_nir.c @@ -514,10 +514,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir) * will not work. */ nir_shader * -brw_postprocess_nir(nir_shader *nir, - const struct gen_device_info *devinfo, +brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, bool is_scalar) { + const struct gen_device_info *devinfo = compiler->devinfo; bool debug_enabled = (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->stage)); @@ -579,10 +579,11 @@ brw_postprocess_nir(nir_shader *nir, nir_shader * brw_nir_apply_sampler_key(nir_shader *nir, - const struct gen_device_info *devinfo, + const struct brw_compiler *compiler, const struct brw_sampler_prog_key_data *key_tex, bool is_scalar) { + const struct gen_device_info *devinfo = compiler->devinfo; nir_lower_tex_options tex_options = { 0 }; /* Iron Lake and prior require lowering of all rectangle textures */ diff --git a/src/mesa/drivers/dri/i965/brw_nir.h b/src/mesa/drivers/dri/i965/brw_nir.h index 3c774d04033..8cfb6c1be68 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.h +++ b/src/mesa/drivers/dri/i965/brw_nir.h @@ -114,7 +114,7 @@ void brw_nir_lower_fs_outputs(nir_shader *nir); void brw_nir_lower_cs_shared(nir_shader *nir); nir_shader *brw_postprocess_nir(nir_shader *nir, - const struct gen_device_info *devinfo, + const struct brw_compiler *compiler, bool is_scalar); bool brw_nir_apply_attribute_workarounds(nir_shader *nir, @@ -126,7 +126,7 @@ bool brw_nir_apply_trig_workarounds(nir_shader *nir); void brw_nir_apply_tcs_quads_workaround(nir_shader *nir); nir_shader *brw_nir_apply_sampler_key(nir_shader *nir, - const struct gen_device_info *devinfo, + const struct brw_compiler *compiler, const struct brw_sampler_prog_key_data *key, bool is_scalar); diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index afab4aa539a..9487a3e1ee8 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1361,10 +1361,10 @@ brw_compile_tes(const struct brw_compiler *compiler, brw_compute_tess_vue_map(&input_vue_map, nir->info->inputs_read, nir->info->patch_inputs_read); - nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar); + nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar); brw_nir_lower_tes_inputs(nir, &input_vue_map); brw_nir_lower_vue_outputs(nir, is_scalar); - nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar); + nir = brw_postprocess_nir(nir, compiler, is_scalar); brw_compute_vue_map(devinfo, &prog_data->base.vue_map, nir->info->outputs_written, diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index b9e592f65f6..d42bcd989da 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -2112,12 +2112,11 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, { const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX]; nir_shader *shader = nir_shader_clone(mem_ctx, src_shader); - shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex, - is_scalar); + shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar); brw_nir_lower_vs_inputs(shader, is_scalar, use_legacy_snorm_formula, key->gl_attrib_wa_flags); brw_nir_lower_vue_outputs(shader, is_scalar); - shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar); + shader = brw_postprocess_nir(shader, compiler, is_scalar); const unsigned *assembly = NULL; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp index 3894a63e323..5f49db11811 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp @@ -615,11 +615,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, &c.input_vue_map, inputs_read, shader->info->separate_shader); - shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex, - is_scalar); + shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar); brw_nir_lower_vue_inputs(shader, is_scalar, &c.input_vue_map); brw_nir_lower_vue_outputs(shader, is_scalar); - shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar); + shader = brw_postprocess_nir(shader, compiler, is_scalar); prog_data->base.clip_distance_mask = ((1 << shader->info->clip_distance_array_size) - 1); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp index b6ff4fda974..92c5d9c5260 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp @@ -467,13 +467,13 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info->outputs_written, nir->info->patch_outputs_written); - nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar); + nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar); brw_nir_lower_vue_inputs(nir, is_scalar, &input_vue_map); brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map); if (key->quads_workaround) brw_nir_apply_tcs_quads_workaround(nir); - nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar); + nir = brw_postprocess_nir(nir, compiler, is_scalar); if (is_scalar) prog_data->instances = DIV_ROUND_UP(nir->info->tcs.vertices_out, 8); -- 2.30.2