From e74047362aee7a86b343738dc9274aea3a3c3e21 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Feb 2020 21:41:53 +0000 Subject: [PATCH] reduce range of b in shift test --- src/ieee754/part/test/test_partsig.py | 36 +++++++++++++++++++++------ 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index 0375f471..8e5ac9fd 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -14,6 +14,20 @@ import unittest import itertools import math +def first_zero(x): + res = 0 + for i in range(16): + if x & (1< 0x{y:X} != 0x{outval:X} ({mod_attr})" + msg = f"{msg_prefix}: 0x{a:X} {mod_attr} 0x{b:X}" + \ + f" => 0x{y:X} != 0x{outval:X}" self.assertEqual(y, outval, msg) if hasattr(module, "%s_carry_out" % mod_attr): c_outval = (yield getattr(module, "%s_carry_out" % mod_attr)) - msg = f"{msg_prefix}: 0x{a:X} + 0x{b:X}" + \ - f" => 0x{carry_result:X} != 0x{c_outval:X}" + \ - " ({mod_attr})" + msg = f"{msg_prefix}: 0x{a:X} {modattr} 0x{b:X}" + \ + f" => 0x{carry_result:X} != 0x{c_outval:X}" self.assertEqual(carry_result, c_outval, msg) - for (test_fn, mod_attr) in ((test_add_fn, "add"), + for (test_fn, mod_attr) in ( + (test_ls_fn, "ls"), + (test_add_fn, "add"), (test_sub_fn, "sub"), (test_neg_fn, "neg"), - (test_ls_fn, "ls"), ): yield part_mask.eq(0) yield from test_op("16-bit", 1, test_fn, mod_attr, 0xFFFF) -- 2.30.2