From e740b60845b56f9bb08ae751d80b058a27c73d5a Mon Sep 17 00:00:00 2001 From: Vadim Girlin Date: Mon, 7 May 2012 12:50:25 +0400 Subject: [PATCH] radeon/llvm: add support for AHSR/LSHR/LSHL instructions Signed-off-by: Vadim Girlin --- src/gallium/drivers/radeon/R600InstrInfo.cpp | 12 +++++++ src/gallium/drivers/radeon/R600InstrInfo.h | 1 + .../drivers/radeon/R600Instructions.td | 8 +++++ .../drivers/radeon/radeon_setup_tgsi_llvm.c | 32 +++++++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 0c7ffc4334d..ed4fcc9ad1e 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -73,10 +73,22 @@ unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const case AMDIL::MOVE_i32: return AMDIL::MOV; case AMDIL::SHR_i32: + return getASHRop(); + case AMDIL::USHR_i32: return getLSHRop(); } } +unsigned R600InstrInfo::getASHRop() const +{ + unsigned gen = TM.getSubtarget().device()->getGeneration(); + if (gen < AMDILDeviceInfo::HD5XXX) { + return AMDIL::ASHR_r600; + } else { + return AMDIL::ASHR_eg; + } +} + unsigned R600InstrInfo::getLSHRop() const { unsigned gen = TM.getSubtarget().device()->getGeneration(); diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h index aedaa9f47f3..701cf7fedee 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.h +++ b/src/gallium/drivers/radeon/R600InstrInfo.h @@ -52,6 +52,7 @@ namespace llvm { bool isTrig(const MachineInstr &MI) const; unsigned getLSHRop() const; + unsigned getASHRop() const; unsigned getMULHI_UINT() const; unsigned getMULLO_UINT() const; unsigned getRECIP_UINT() const; diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index 0a73b5cfbf0..9df057025f2 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -535,6 +535,12 @@ class LSHR_Common inst> : R600_2OP < let AMDILOp = AMDILInst.USHR_i32; } +class ASHR_Common inst> : R600_2OP < + inst, "ASHR $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.SHR_i32; +} + class MULHI_INT_Common inst> : R600_2OP < inst, "MULHI_INT $dst, $src0, $src1", [] >{ @@ -645,6 +651,7 @@ let Gen = AMDGPUGen.R600 in { def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; def SIN_r600 : SIN_Common<0x6E>; def COS_r600 : COS_Common<0x6F>; + def ASHR_r600 : ASHR_Common<0x70>; def LSHR_r600 : LSHR_Common<0x71>; def LSHL_r600 : LSHL_Common<0x72>; def MULLO_INT_r600 : MULLO_INT_Common<0x73>; @@ -815,6 +822,7 @@ class TRIG_eg : Pat< let Gen = AMDGPUGen.EG_CAYMAN in { def MULADD_eg : MULADD_Common<0x14>; + def ASHR_eg : ASHR_Common<0x15>; def LSHR_eg : LSHR_Common<0x16>; def LSHL_eg : LSHL_Common<0x17>; def CNDE_eg : CNDE_Common<0x19>; diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c index fe5d1b8279f..2932bdd9490 100644 --- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c @@ -533,6 +533,35 @@ static void tex_fetch_args( emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); } +static void emit_shl( + const struct lp_build_tgsi_action * action, + struct lp_build_tgsi_context * bld_base, + struct lp_build_emit_data * emit_data) +{ + LLVMBuilderRef builder = bld_base->base.gallivm->builder; + emit_data->output[emit_data->chan] = LLVMBuildShl(builder, + emit_data->args[0], emit_data->args[1], ""); +} + +static void emit_ushr( + const struct lp_build_tgsi_action * action, + struct lp_build_tgsi_context * bld_base, + struct lp_build_emit_data * emit_data) +{ + LLVMBuilderRef builder = bld_base->base.gallivm->builder; + emit_data->output[emit_data->chan] = LLVMBuildLShr(builder, + emit_data->args[0], emit_data->args[1], ""); +} +static void emit_ishr( + const struct lp_build_tgsi_action * action, + struct lp_build_tgsi_context * bld_base, + struct lp_build_emit_data * emit_data) +{ + LLVMBuilderRef builder = bld_base->base.gallivm->builder; + emit_data->output[emit_data->chan] = LLVMBuildAShr(builder, + emit_data->args[0], emit_data->args[1], ""); +} + static void emit_immediate(struct lp_build_tgsi_context * bld_base, const struct tgsi_full_immediate *imm) { @@ -606,6 +635,9 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) lp_set_default_actions(bld_base); + bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl; + bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr; + bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr; bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx"; bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args; bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy"; -- 2.30.2