From e7598c5a628cd86e76bf53b9467934357d890e5c Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Sat, 8 Dec 2018 21:50:36 -0800 Subject: [PATCH] intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar region When RepCtrl is set, the swizzle field is ignored by the hardware. In order to ensure a 1-to-1 correspondence between the human-readable disassembly and the binary instruction encoding always set the swizzle to XXXX (all zeros) when it is unused due to RepCtrl Signed-off-by: Sagar Ghuge Reviewed-by: Matt Turner --- src/intel/compiler/brw_eu_emit.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 4630b83b1a0..483037345e9 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -833,7 +833,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \ struct brw_reg src0, \ struct brw_reg src1, \ struct brw_reg src2) \ -{ \ +{ \ + if (p->current->access_mode == BRW_ALIGN_16) { \ + if (src0.vstride == BRW_VERTICAL_STRIDE_0) \ + src0.swizzle = BRW_SWIZZLE_XXXX; \ + if (src1.vstride == BRW_VERTICAL_STRIDE_0) \ + src1.swizzle = BRW_SWIZZLE_XXXX; \ + if (src2.vstride == BRW_VERTICAL_STRIDE_0) \ + src2.swizzle = BRW_SWIZZLE_XXXX; \ + } \ return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ } @@ -854,6 +862,15 @@ brw_inst *brw_##OP(struct brw_codegen *p, \ assert(src0.type == BRW_REGISTER_TYPE_DF); \ assert(src1.type == BRW_REGISTER_TYPE_DF); \ assert(src2.type == BRW_REGISTER_TYPE_DF); \ + } \ + \ + if (p->current->access_mode == BRW_ALIGN_16) { \ + if (src0.vstride == BRW_VERTICAL_STRIDE_0) \ + src0.swizzle = BRW_SWIZZLE_XXXX; \ + if (src1.vstride == BRW_VERTICAL_STRIDE_0) \ + src1.swizzle = BRW_SWIZZLE_XXXX; \ + if (src2.vstride == BRW_VERTICAL_STRIDE_0) \ + src2.swizzle = BRW_SWIZZLE_XXXX; \ } \ return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ } -- 2.30.2