From e75ca29b19e230bc829a369c7de9cbadb629f5a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 11:26:54 -0800
Subject: [PATCH] Add test: 'Warning: ignoring initial value on non-register:
 \o'

---
 tests/sat/initval.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 2079d2f34..337aa9343 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -2,3 +2,13 @@ read_verilog -sv initval.v
 proc;;
 
 sat -seq 10 -prove-asserts
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, output o, p);
+(* init = 1'bx *)
+wire p = o;
+$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
+endmodule
+EOT
+sat -seq 1
-- 
2.30.2