From e76d3ab8b346cb1bd8d0155f78617c1065e8afe6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 21 Apr 2022 12:58:59 +0100 Subject: [PATCH] --- openpower/sv/biginteger/analysis.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn index 5ba008fca..1be393b7c 100644 --- a/openpower/sv/biginteger/analysis.mdwn +++ b/openpower/sv/biginteger/analysis.mdwn @@ -18,7 +18,10 @@ a straightforward big-integer add or subtract. Vectorised `adde` or `addex` is perfectly sufficient to produce arbitrary-length big-integer add due to the rules set in SVP64 that all Vector Operations are directly equivalent to the strict Program Order Execution of -their element-level operations. +their element-level operations. Assuming that the two bigints (or +a part thereof) have been loaded into sequentially-contiguous +registers, with the least-significant bits being in the lowest-numbered +register in each case: R0,CA = A0+B0+CA adde r0,a0,b0 | @@ -43,6 +46,12 @@ in back-end hardware that need only read the first incoming XER.CA and only store the last XER.CA. The size of the underlying back-end SIMD ALU is entirely at the discretion of the implementer. +If there is pressure on the register file (multi-million-digit big integers) +then a partial-sum may be carried out with LD and ST in a standard +Cray-style Vector Loop: + + + # Multiply Long-multiply, assuming an O(N^2) algorithm, is performed by summing -- 2.30.2