From e78c4f5d7b8c1c03d1b20ceb021eb5fd99c19dd2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Sep 2021 20:16:23 +0100 Subject: [PATCH] Revert "move coresync clock synchronisation into HDLRunner" This reverts commit 8a51f6944fa6c5185285b0139f5b419fb68aa145. --- src/soc/simple/test/test_runner.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 09481697..e4e109ec 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -201,10 +201,6 @@ class HDLRunner(StateRunner): comb += self.issuer.pc_i.data.eq(self.pc_i) comb += self.issuer.svstate_i.data.eq(self.svstate_i) - # run core clock at same rate as test clock - intclk = ClockSignal("coresync") - comb += intclk.eq(ClockSignal()) - def prepare_for_test(self, test): self.test = test @@ -384,6 +380,10 @@ class TestRunner(FHDLTestCase): if self.run_sim: simrun = SimRunner(self, m, pspec) + # run core clock at same rate as test clock + intclk = ClockSignal("coresync") + comb += intclk.eq(ClockSignal()) + # nmigen Simulation - everything runs around this, so it # still has to be created. sim = Simulator(m) -- 2.30.2