From e79132c8374e9fc42b30eb8b512fb4ba71323341 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Wed, 5 Aug 2020 16:37:38 +0200 Subject: [PATCH] Fix code styling --- gram/core/multiplexer.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py index f109225..3a01278 100644 --- a/gram/core/multiplexer.py +++ b/gram/core/multiplexer.py @@ -289,8 +289,7 @@ class Multiplexer(Elaboratable): m.submodules.choose_cmd = choose_cmd = _CommandChooser(requests) m.submodules.choose_req = choose_req = _CommandChooser(requests) for i, request in enumerate(requests): - m.d.comb += request.ready.eq( - choose_cmd.ready[i] | choose_req.ready[i]) + m.d.comb += request.ready.eq(choose_cmd.ready[i] | choose_req.ready[i]) if settings.phy.nphases == 1: # When only 1 phase, use choose_req for all requests choose_cmd = choose_req @@ -332,9 +331,9 @@ class Multiplexer(Elaboratable): # Read/write turnaround -------------------------------------------------------------------- reads = Signal(len(requests)) - m.d.comb += reads.eq(Cat([req.valid & req.is_read for req in requests])) + m.d.comb += reads.eq(Cat([(req.valid & req.is_read) for req in requests])) writes = Signal(len(requests)) - m.d.comb += writes.eq(Cat([req.valid & req.is_write for req in requests])) + m.d.comb += writes.eq(Cat([(req.valid & req.is_write) for req in requests])) # Anti Starvation -------------------------------------------------------------------------- m.submodules.read_antistarvation = read_antistarvation = _AntiStarvation(settings.read_time) @@ -399,8 +398,7 @@ class Multiplexer(Elaboratable): m.d.comb += steerer.sel[i].eq(STEER_CMD) with m.If(settings.phy.nphases == 1): - m.d.comb += choose_req.cmd.ready.eq( - cas_allowed & (~choose_req.activate() | ras_allowed)) + m.d.comb += choose_req.cmd.ready.eq(cas_allowed & (~choose_req.activate() | ras_allowed)) with m.Else(): m.d.comb += [ choose_cmd.want_activates.eq(ras_allowed), -- 2.30.2