From e79b2e3fefd9cf6ed5d3e671fbb50c989266afa4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 29 Apr 2016 19:05:23 +0200 Subject: [PATCH] boards/targets: SDRAM modules are now litedram.modules --- litex/boards/targets/de0nano.py | 2 +- litex/boards/targets/kc705.py | 2 +- litex/boards/targets/minispartan6.py | 2 +- litex/boards/targets/sim.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 7fb9d625..17da0e72 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -8,7 +8,7 @@ from litex.boards.platforms import de0nano from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.settings import IS42S16160 +from litedram.modules import IS42S16160 from litedram.phy import GENSDRPHY diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 65500af7..9139be8e 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -11,7 +11,7 @@ from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.settings import MT8JTF12864 +from litedram.modules import MT8JTF12864 from litedram.phy import k7ddrphy from liteeth.phy import LiteEthPHY diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 04443bde..7c622367 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -10,7 +10,7 @@ from litex.boards.platforms import minispartan6 from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.settings import AS4C16M16 +from litedram.modules import AS4C16M16 from litedram.phy import GENSDRPHY diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index b18996ea..0d083112 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -12,7 +12,7 @@ from litex.soc.integration.builder import * from litex.soc.cores import uart from litex.soc.integration.soc_core import mem_decoder -from litedram.settings import PhySettings, IS42S16160 +from litedram.modules import PhySettings, IS42S16160 from litedram.model import SDRAMPHYModel from liteeth.phy.model import LiteEthPHYModel -- 2.30.2