From e7a1636889dec63a65723dc4df71d1970b013116 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 18 Feb 2019 14:33:36 +0000 Subject: [PATCH] dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini Reviewed-by: Anouk Van Laer Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg --- src/arch/arm/isa.cc | 1 + src/dev/arm/Gic.py | 5 +++++ src/dev/arm/RealView.py | 2 +- src/dev/arm/gic_v3.hh | 1 + src/dev/arm/gic_v3_cpu_interface.cc | 8 +++++++- src/dev/arm/gic_v3_cpu_interface.hh | 9 +++++++-- 6 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 38fbae142..42e1cba3f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -403,6 +403,7 @@ ISA::startup(ThreadContext *tc) haveGICv3CPUInterface = true; gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); gicv3CpuInterface->setISA(this); + gicv3CpuInterface->setThreadContext(tc); } } } diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 014d4dfe4..6f7c8d973 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -173,3 +173,8 @@ class Gicv3(BaseGic): "Delay for PIO r/w to redistributors") it_lines = Param.UInt32(1020, "Number of interrupt lines supported (max = 1020)") + + maint_int = Param.ArmInterruptPin( + "HV maintenance interrupt." + "ARM strongly recommends that maintenance interrupts " + "are configured to use INTID 25 (PPI Interrupt).") diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index 41d5fc893..908644899 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -1083,7 +1083,7 @@ class VExpress_GEM5_V1(VExpress_GEM5_V1_Base): ] class VExpress_GEM5_V2_Base(VExpress_GEM5_Base): - gic = Gicv3() + gic = Gicv3(maint_int=ArmPPI(num=25)) def _on_chip_devices(self): return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [ diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh index e38d9ba03..3a1a8761b 100644 --- a/src/dev/arm/gic_v3.hh +++ b/src/dev/arm/gic_v3.hh @@ -41,6 +41,7 @@ class Gicv3Redistributor; class Gicv3 : public BaseGic { protected: + friend class Gicv3CPUInterface; typedef Gicv3Params Params; Gicv3Distributor * distributor; diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index 8cbc77a0b..577442efa 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -64,6 +64,12 @@ Gicv3CPUInterface::reset() hppi.prio = 0xff; } +void +Gicv3CPUInterface::setThreadContext(ThreadContext *tc) +{ + maintenanceInterrupt = gic->params()->maint_int->get(tc); +} + bool Gicv3CPUInterface::getHCREL2FMO() const { @@ -1985,7 +1991,7 @@ Gicv3CPUInterface::virtualUpdate() if (ich_hcr_el2.En) { if (maintenanceInterruptStatus()) { - redistributor->sendPPInt(25); + maintenanceInterrupt->raise(); } } diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index 271be87a7..931eb1df8 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -51,6 +51,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable Gicv3Distributor * distributor; uint32_t cpuId; + ArmInterruptPin *maintenanceInterrupt; + BitUnion64(ICC_CTLR_EL1) Bitfield<63, 20> res0_3; Bitfield<19> ExtRange; @@ -307,10 +309,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable bool isEOISplitMode() const; bool isSecureBelowEL3() const; ICH_MISR_EL2 maintenanceInterruptStatus() const; - RegVal readMiscReg(int misc_reg) override; void reset(); void serialize(CheckpointOut & cp) const override; - void setMiscReg(int misc_reg, RegVal val) override; void unserialize(CheckpointIn & cp) override; void update(); void virtualActivateIRQ(uint32_t lrIdx); @@ -329,6 +329,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable void init(); void initState(); + + public: // BaseISADevice + RegVal readMiscReg(int misc_reg) override; + void setMiscReg(int misc_reg, RegVal val) override; + void setThreadContext(ThreadContext *tc) override; }; #endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__ -- 2.30.2