From e7a6932719eb6813e47e4696bb9b41b03feb01e5 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 8 Sep 2021 12:31:40 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index b4baaf078..b6540eb84 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -37,15 +37,15 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations: | 4 | 5 | 19-20 | 21 | 22 23 | description | | - | - | ----- | --- |---------|----------------- | -|dz |VLi| 01 | inv | CR-bit | Ffirst 3-bit mode | -|sz |VLi| 01 | inv | dz Rc1 | Ffirst 5-bit mode | | / | / | 00 | 0 | dz sz | normal mode | | / | / | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | | / | / | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 | | / | / | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 | +|dz |VLi| 01 | inv | CR-bit | Ffirst 3-bit mode | +|sz |VLi| 01 | inv | dz Rc1 | Ffirst 5-bit mode | | / | / | 10 | / | / / | RESERVED | -|dz | / | 11 | inv | CR-bit | 3-bit pred-result CR sel | -| / | / | 11 | inv | dz sz | 5-bit pred-result z/nonz | +|sz |SNZ| 11 | inv | CR-bit | 3-bit pred-result CR sel | +| / |SNZ| 11 | inv | dz sz | 5-bit pred-result z/nonz | Fields: -- 2.30.2