From e7a75d524344fec5a2e08a5e2b0ee2b0315b447f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Oct 2018 05:14:01 +0100 Subject: [PATCH] add backslash --- simple_v_extension/specification.mdwn | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index ab47af637..6af92df97 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -686,7 +686,7 @@ do not change in SV, however just as with C.MV it is important to note that dual-predication is possible. Using the template outlined in the section "Vectorised dual-op instructions", the pseudo-code covering scalar-scalar, scalar-vector, vector-scalar and vector-vector applies, -where SCALAR_OPERATION is as follows, exactly as for a standard +where SCALAR\_OPERATION is as follows, exactly as for a standard scalar RV LOAD operation: srcbase = ireg[rs+i]; @@ -695,14 +695,8 @@ scalar RV LOAD operation: ## Compressed Stack LOAD / STORE Instructions - - -[[!table data=""" -15 13 | 12 10 | 9 7 | 6 5 | 4 2 | 1 0 | -funct3 | imm | rs10 | imm | rd0 | op | -3 | 3 | 3 | 2 | 3 | 2 | -C.LWSP | offset[5:3] | base | offset[2|6] | dest | C0 | -"""]] +C.LWSP / C.SWSP and floating-point etc. are also source-dest twin-predicated, +where it is implicit in C.LWSP/FLWSP that x2 is the source register. ## Compressed LOAD / STORE Instructions -- 2.30.2