From e7a984a4dfc3248a23a752c8e92a7370c70af87a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 31 May 2017 11:45:58 +0200 Subject: [PATCH] Add dff2ff.v techmap file --- techlibs/common/Makefile.inc | 1 + techlibs/common/dff2ff.v | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 techlibs/common/dff2ff.v diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 236d6c551..ab961ac0b 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -24,5 +24,6 @@ $(eval $(call add_share_file,share,techlibs/common/simcells.v)) $(eval $(call add_share_file,share,techlibs/common/techmap.v)) $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v)) $(eval $(call add_share_file,share,techlibs/common/adff2dff.v)) +$(eval $(call add_share_file,share,techlibs/common/dff2ff.v)) $(eval $(call add_share_file,share,techlibs/common/cells.lib)) diff --git a/techlibs/common/dff2ff.v b/techlibs/common/dff2ff.v new file mode 100644 index 000000000..2dc4d20d3 --- /dev/null +++ b/techlibs/common/dff2ff.v @@ -0,0 +1,14 @@ +(* techmap_celltype = "$dff" *) +module dff2ff (CLK, D, Q); + parameter WIDTH = 1; + parameter CLK_POLARITY = 1; + + input CLK; + input [WIDTH-1:0] D; + output reg [WIDTH-1:0] Q; + + wire [1023:0] _TECHMAP_DO_ = "proc;;"; + + always @($global_clock) + Q <= D; +endmodule -- 2.30.2