From e7bf78abae3035ce4173dedf033a37119b39072a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 18:45:42 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 718ae8457..5bedbd7ea 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -701,7 +701,7 @@ Fields are as follows: * MSB..LSB: the bit field showing how the register opcode field combines with EXTRA to give (extend) the register number (GPR) -| Value | Mode | Range/Inc | 6..0 | +| Value | Mode | Range/Inc | 6..0 | |-----------|-------|---------------|---------------------| | 000 | Scalar | `r0-r31`/1 | `0b00 RA` | | 001 | Scalar | `r32-r63`/1 | `0b01 RA` | @@ -717,8 +717,8 @@ Fields are as follows: If EXTRA2 is zero will map to "scalar identity behaviour" i.e Scalar Power ISA register naming: -| Value | Mode | Range/inc | 6..0 | -|-----------|-------|---------------|-----------| +| Value | Mode | Range/inc | 6..0 | +|----------|-------|---------------|-----------| | 00 | Scalar | `r0-r31`/1 | `0b00 RA` | | 01 | Scalar | `r32-r63`/1 | `0b01 RA` | | 10 | Vector | `r0-r124`/4 | `RA 0b00` | @@ -937,11 +937,11 @@ sets up a chain of Register Hazard Dependencies, whereas Parallel Reduce [[sv/remap]] deliberately issues a Tree-Schedule of operations that may be parallelised. -## Fail-on-first +## Data-dependent Fail-on-first -Data-dependent fail-on-first has two distinct variants: one for LD/ST, -the other for arithmetic operations (actually, CR-driven). Note in -each case the assumption is that vector elements are required to appear +Data-dependent fail-on-first is very different from LD/ST Fail-First +(also known as Fault-First) and is actually CR-field-driven. +Vector elements are required to appear to be executed in sequential Program Order. When REMAP is not active, element 0 would be the first. @@ -993,6 +993,17 @@ not so limited. Thus it is possible to use for example `sv.cror/ff=gt/vli *0,*0,*0`, which is not a `nop` because it allows Fail-First Mode to perform a test and truncate VL.* +*Hardware implementor's note: effective Sequential Program Order must be preserved. +Speculative Execution is perfectly permitted as long as the speculative elements +are held back from writing to register files (kept in Resevation Stations), +until such time as the relevant +CR Field bit(s) has been analysed. All Speculative elements sequentially beyond the +test-failure point **MUST** be cancelled. This is no different from standard +Out-of-Order Execution and the modification effort to efficiently support +Data-Dependent Fail-First within a pre-existing Multi-Issue Out-of-Order Engine +is anticipated to be minimal. In-Order systems on the other hand are expected, +unavoidably, to be low-performance*. + Two extremely important aspects of ffirst are: * LDST ffirst may never set VL equal to zero. This because on the first -- 2.30.2