From e7c356866e13438711aa0915f9b58fa630fb1917 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 18 Jul 2019 15:51:28 +0200 Subject: [PATCH] radv: change a bunch of >= GFX9 to == GFX9 Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- src/amd/vulkan/radv_device.c | 2 +- src/amd/vulkan/radv_image.c | 10 +++++----- src/amd/vulkan/si_cmd_buffer.c | 12 ++++++------ 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b4301c0da15..b6ac14f63a9 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1294,7 +1294,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, cb->cb_color_attrib2); radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4, cb->cb_color_attrib3); - } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32)); @@ -1432,7 +1432,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32); - } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3); radeon_emit(cmd_buffer->cs, ds->db_htile_data_base); radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32)); @@ -2508,7 +2508,7 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, draw_vertex_count); if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) { - if (info->chip_class >= GFX9) { + if (info->chip_class == GFX9) { radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs, R_030960_IA_MULTI_VGT_PARAM, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a4ec2e4ac16..8a5d4ac8cfd 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2499,7 +2499,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue, radv_emit_shader_pointer(queue->device, cs, regs[i], va, true); } - } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) { + } else if (queue->device->physical_device->rad_info.chip_class == GFX9) { uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, R_00B130_SPI_SHADER_USER_DATA_VS_0, R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS, diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 4d3ed71c23c..09413333cbb 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -522,7 +522,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, } state[7] = meta_va >> 16; - } else if (chip_class >= GFX9) { + } else if (chip_class == GFX9) { state[3] &= C_008F1C_SW_MODE; state[4] &= C_008F20_PITCH; @@ -787,7 +787,7 @@ si_make_texture_descriptor(struct radv_device *device, } /* S8 with either Z16 or Z32 HTILE need a special format. */ - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.chip_class == GFX9 && vk_format == VK_FORMAT_S8_UINT && radv_image_is_tc_compat_htile(image)) { if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) @@ -828,7 +828,7 @@ si_make_texture_descriptor(struct radv_device *device, state[6] = 0; state[7] = 0; - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.chip_class == GFX9) { unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle); /* Depth is the last accessible layer on Gfx9. @@ -874,7 +874,7 @@ si_make_texture_descriptor(struct radv_device *device, va = gpu_address + image->offset + image->fmask.offset; - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.chip_class == GFX9) { fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK; switch (image->info.samples) { case 2: @@ -924,7 +924,7 @@ si_make_texture_descriptor(struct radv_device *device, fmask_state[6] = 0; fmask_state[7] = 0; - if (device->physical_device->rad_info.chip_class >= GFX9) { + if (device->physical_device->rad_info.chip_class == GFX9) { fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 0efa169d674..21a90cb2514 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -244,7 +244,7 @@ si_emit_graphics(struct radv_physical_device *physical_device, radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0); radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0); radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0); - } else if (physical_device->rad_info.chip_class >= GFX9) { + } else if (physical_device->rad_info.chip_class == GFX9) { radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0); @@ -1112,7 +1112,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } - if (chip_class >= GFX9 && flush_cb_db) { + if (chip_class == GFX9 && flush_cb_db) { unsigned cb_db_event, tc_flags; /* Set the CB/DB flush event. */ @@ -1184,7 +1184,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, if ((flush_bits & RADV_CMD_FLAG_INV_L2) || (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) { - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, + si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | @@ -1199,7 +1199,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, * WB doesn't work without NC. */ si_emit_acquire_mem(cs, is_mec, - chip_class >= GFX9, + chip_class == GFX9, cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); @@ -1207,7 +1207,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, } if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) { si_emit_acquire_mem(cs, is_mec, - chip_class >= GFX9, + chip_class == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; @@ -1218,7 +1218,7 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, * Therefore, it should be last. Done in PFP. */ if (cp_coher_cntl) - si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9, cp_coher_cntl); + si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); -- 2.30.2