From e7c7ab8fc06b3accc7f6d98313ec09e54a605124 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sat, 16 Feb 2019 13:45:17 -0800
Subject: [PATCH] expose command to not skip 'internal' wires beginning with
 '$'

---
 passes/sat/expose.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 809345486..3add9a9eb 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -42,7 +42,7 @@ struct dff_map_bit_info_t {
 
 bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
 {
-	if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
+	if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name))
 		return false;
 	if (wire->port_input)
 		return false;
-- 
2.30.2