From e7dcf3ce1b085756e71485148ccf48a9e47644ee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 14 Nov 2020 18:41:29 +0000 Subject: [PATCH] simplify litex-core wishbone interfaces --- src/soc/interrupts/xics.py | 4 ++-- src/soc/litex/florent/libresoc/core.py | 20 ++++++++++++++------ src/soc/minerva/wishbone.py | 12 ++++++++---- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py index a0a852d3..ede33a1b 100644 --- a/src/soc/interrupts/xics.py +++ b/src/soc/interrupts/xics.py @@ -78,7 +78,7 @@ class XICS_ICP(Elaboratable): spec.addr_wid = 30 spec.mask_wid = 4 spec.reg_wid = 32 - self.bus = Record(make_wb_layout(spec), name="icp_wb") + self.bus = Record(make_wb_layout(spec, cti=False), name="icp_wb") self.ics_i = ICS2ICP("ics_i") self.core_irq_o = Signal() @@ -232,7 +232,7 @@ class XICS_ICS(Elaboratable): spec.addr_wid = 30 spec.mask_wid = 4 spec.reg_wid = 32 - self.bus = Record(make_wb_layout(spec), name="ics_wb") + self.bus = Record(make_wb_layout(spec, cti=False), name="ics_wb") self.int_level_i = Signal(SRC_NUM) self.icp_o = ICS2ICP("icp_o") diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 842a9f6e..55a84c97 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -29,9 +29,12 @@ def make_wb_bus(prefix, obj, simple=False): res['i_%s__%s' % (prefix, i)] = getattr(obj, i) return res -def make_wb_slave(prefix, obj): +def make_wb_slave(prefix, obj, simple=False): res = {} - for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']: + inpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel'] + if not simple: + inpins += ['cti', 'bte'] + for i in inpins: res['i_%s__%s' % (prefix, i)] = getattr(obj, i) for o in ['ack', 'err', 'dat_r']: res['o_%s__%s' % (prefix, o)] = getattr(obj, o) @@ -250,14 +253,19 @@ class LibreSoC(CPU): self.cpu_params['o_pll_lck_o'] = self.pll_lck_o # add wishbone buses to cpu params - self.cpu_params.update(make_wb_bus("ibus", ibus)) - self.cpu_params.update(make_wb_bus("dbus", dbus)) - self.cpu_params.update(make_wb_slave("ics_wb", ics)) - self.cpu_params.update(make_wb_slave("icp_wb", icp)) + self.cpu_params.update(make_wb_bus("ibus", ibus, True)) + self.cpu_params.update(make_wb_bus("dbus", dbus, True)) + self.cpu_params.update(make_wb_slave("ics_wb", ics, True)) + self.cpu_params.update(make_wb_slave("icp_wb", icp, True)) if "testgpio" in variant: self.cpu_params.update(make_wb_slave("gpio_wb", gpio)) if jtag_en: self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True)) + # and set ibus advanced tags to zero (disable) + self.cpu_params['i_ibus__cti'] = 0 + self.cpu_params['i_ibus__bte'] = 0 + self.cpu_params['i_dbus__cti'] = 0 + self.cpu_params['i_dbus__bte'] = 0 if variant == 'ls180': # urr yuk. have to expose iopads / pins from core to litex diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py index ba08531e..f84a01cc 100644 --- a/src/soc/minerva/wishbone.py +++ b/src/soc/minerva/wishbone.py @@ -14,12 +14,12 @@ class Cycle: END = 7 -def make_wb_layout(spec): +def make_wb_layout(spec, cti=True): addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask badwid = spec.addr_wid-adr_lsbs # MSBs (not covered by mask) - return [ + res = [ ("adr", badwid , DIR_FANOUT), ("dat_w", data_wid, DIR_FANOUT), ("dat_r", data_wid, DIR_FANIN), @@ -28,10 +28,14 @@ def make_wb_layout(spec): ("stb", 1, DIR_FANOUT), ("ack", 1, DIR_FANIN), ("we", 1, DIR_FANOUT), - ("cti", 3, DIR_FANOUT), - ("bte", 2, DIR_FANOUT), ("err", 1, DIR_FANIN) ] + if not cti: + return res + return res + [ + ("cti", 3, DIR_FANOUT), + ("bte", 2, DIR_FANOUT), + ] class WishboneArbiter(Elaboratable): -- 2.30.2