From e8125348b3d13a2e96ae389efc2a16a1e8e34ea3 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Wed, 28 Jul 2010 19:08:04 -0700
Subject: [PATCH] [sim,xcc] Changed instruction format to RISC-V

Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.
---
 riscv/applink.cc     |    2 +-
 riscv/common.h       |    2 +
 riscv/decode.h       |   47 +-
 riscv/execute.h      | 1636 +++++++++++++++++++++++++++---------------
 riscv/insns/add.h    |    2 +-
 riscv/insns/addi.h   |    2 +-
 riscv/insns/and.h    |    2 +-
 riscv/insns/andi.h   |    2 +-
 riscv/insns/beq.h    |    2 +-
 riscv/insns/ble.h    |    2 +-
 riscv/insns/bleu.h   |    2 +-
 riscv/insns/blt.h    |    2 +-
 riscv/insns/bltu.h   |    2 +-
 riscv/insns/bne.h    |    2 +-
 riscv/insns/dadd.h   |    2 +-
 riscv/insns/daddi.h  |    2 +-
 riscv/insns/ddiv.h   |    2 +-
 riscv/insns/ddivu.h  |    2 +-
 riscv/insns/di.h     |    2 +-
 riscv/insns/div.h    |    2 +-
 riscv/insns/divu.h   |    2 +-
 riscv/insns/dmfc0.h  |   16 +-
 riscv/insns/dmtc0.h  |   10 +-
 riscv/insns/dmul.h   |    2 +-
 riscv/insns/dmulh.h  |    4 +
 riscv/insns/dmulhu.h |    2 +
 riscv/insns/drem.h   |    2 +
 riscv/insns/dremu.h  |    2 +
 riscv/insns/dsll.h   |    2 +-
 riscv/insns/dsll32.h |    2 +-
 riscv/insns/dsllv.h  |    2 +-
 riscv/insns/dsra.h   |    2 +-
 riscv/insns/dsra32.h |    2 +-
 riscv/insns/dsrav.h  |    2 +-
 riscv/insns/dsrl.h   |    2 +-
 riscv/insns/dsrl32.h |    2 +-
 riscv/insns/dsrlv.h  |    2 +-
 riscv/insns/dsub.h   |    2 +-
 riscv/insns/ei.h     |    2 +-
 riscv/insns/jalr_c.h |    3 +
 riscv/insns/jalr_j.h |    1 +
 riscv/insns/jalr_r.h |    1 +
 riscv/insns/lb.h     |    2 +-
 riscv/insns/lbu.h    |    2 +-
 riscv/insns/ld.h     |    2 +-
 riscv/insns/lh.h     |    2 +-
 riscv/insns/lhu.h    |    2 +-
 riscv/insns/lui.h    |    2 +-
 riscv/insns/lw.h     |    2 +-
 riscv/insns/lwu.h    |    2 +-
 riscv/insns/mfc0.h   |   16 +-
 riscv/insns/movn.h   |    2 +-
 riscv/insns/movz.h   |    2 +-
 riscv/insns/mtc0.h   |   10 +-
 riscv/insns/mul.h    |    2 +-
 riscv/insns/mulh.h   |    2 +
 riscv/insns/mulhu.h  |    2 +
 riscv/insns/nor.h    |    2 +-
 riscv/insns/or.h     |    2 +-
 riscv/insns/ori.h    |    2 +-
 riscv/insns/rdpc.h   |    1 +
 riscv/insns/rem.h    |    2 +
 riscv/insns/remu.h   |    2 +
 riscv/insns/sb.h     |    2 +-
 riscv/insns/sd.h     |    2 +-
 riscv/insns/sh.h     |    2 +-
 riscv/insns/sll.h    |    2 +-
 riscv/insns/sllv.h   |    2 +-
 riscv/insns/slori.h  |    1 +
 riscv/insns/slt.h    |    2 +-
 riscv/insns/slti.h   |    2 +-
 riscv/insns/sltiu.h  |    2 +-
 riscv/insns/sltu.h   |    2 +-
 riscv/insns/sra.h    |    2 +-
 riscv/insns/srav.h   |    2 +-
 riscv/insns/srl.h    |    2 +-
 riscv/insns/srlv.h   |    2 +-
 riscv/insns/sub.h    |    2 +-
 riscv/insns/sw.h     |    2 +-
 riscv/insns/xor.h    |    2 +-
 riscv/insns/xori.h   |    2 +-
 riscv/mmu.h          |    2 +-
 riscv/processor.cc   |    5 +-
 83 files changed, 1223 insertions(+), 668 deletions(-)
 create mode 100644 riscv/insns/dmulh.h
 create mode 100644 riscv/insns/dmulhu.h
 create mode 100644 riscv/insns/drem.h
 create mode 100644 riscv/insns/dremu.h
 create mode 100644 riscv/insns/jalr_c.h
 create mode 100644 riscv/insns/jalr_j.h
 create mode 100644 riscv/insns/jalr_r.h
 create mode 100644 riscv/insns/mulh.h
 create mode 100644 riscv/insns/mulhu.h
 create mode 100644 riscv/insns/rdpc.h
 create mode 100644 riscv/insns/rem.h
 create mode 100644 riscv/insns/remu.h
 create mode 100644 riscv/insns/slori.h

diff --git a/riscv/applink.cc b/riscv/applink.cc
index 0937067..d8fddad 100644
--- a/riscv/applink.cc
+++ b/riscv/applink.cc
@@ -80,7 +80,7 @@ int appserver_link_t::wait_for_packet()
   {
     packet p;
     int bytes = read(fromhost_fd,&p,sizeof(p));
-    if(bytes < offsetof(packet,data))
+    if(bytes < (signed)offsetof(packet,data))
       throw io_error("read failed");
   
     if(p.seqno != seqno)
diff --git a/riscv/common.h b/riscv/common.h
index 447d631..cbb8e95 100644
--- a/riscv/common.h
+++ b/riscv/common.h
@@ -20,4 +20,6 @@
       print_and_die(__str); \
     } } while(0)
 
+#define static_assert(x)	switch (x) case 0: case (x):
+
 #endif
diff --git a/riscv/decode.h b/riscv/decode.h
index ded38ab..40c79f7 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2,12 +2,15 @@
 #define _RISCV_DECODE_H
 
 #include <stdint.h>
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
 
 #define support_64bit 1
 typedef int64_t sreg_t;
 typedef uint64_t reg_t;
 
-const int OPCODE_BITS = 6;
+const int OPCODE_BITS = 7;
+const int JTYPE_OPCODE_BITS = 5;
 
 const int GPR_BITS = 8*sizeof(reg_t);
 const int GPRID_BITS = 5;
@@ -17,10 +20,11 @@ const int FPR_BITS = 64;
 const int FPRID_BITS = 5;
 const int NFPR = 1 << FPRID_BITS;
 
-const int IMM_BITS = 16;
-const int TARGET_BITS = 26;
-const int SHAMT_BITS = 5;
-const int FUNCT_BITS = 6;
+const int IMM_BITS = 12;
+const int TARGET_BITS = 27;
+const int SHAMT_BITS = 6;
+const int FUNCT_BITS = 3;
+const int BIGIMM_BITS = 20;
 
 #define SR_ET    0x0000000000000001ULL
 #define SR_PS    0x0000000000000004ULL
@@ -35,24 +39,33 @@ const int FUNCT_BITS = 6;
 struct itype_t
 {
   unsigned imm : IMM_BITS;
-  unsigned rt : GPRID_BITS;
-  unsigned rs : GPRID_BITS;
+  unsigned funct : FUNCT_BITS;
+  unsigned rb : GPRID_BITS;
+  unsigned ra : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct jtype_t
 {
   unsigned target : TARGET_BITS;
-  unsigned opcode : OPCODE_BITS;
+  unsigned jump_opcode : JTYPE_OPCODE_BITS;
 };
 
 struct rtype_t
 {
-  unsigned funct : FUNCT_BITS;
+  unsigned rc : GPRID_BITS;
   unsigned shamt : SHAMT_BITS;
-  unsigned rd : GPRID_BITS;
+  unsigned unused : 1;
+  unsigned funct : FUNCT_BITS;
+  unsigned rb : GPRID_BITS;
+  unsigned ra : GPRID_BITS;
+  unsigned opcode : OPCODE_BITS;
+};
+
+struct btype_t
+{
+  unsigned bigimm : BIGIMM_BITS;
   unsigned rt : GPRID_BITS;
-  unsigned rs : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -61,19 +74,21 @@ union insn_t
   itype_t itype;
   jtype_t jtype;
   rtype_t rtype;
+  btype_t btype;
   uint32_t bits;
 };
 
 // helpful macros, etc
-#define RS R[insn.rtype.rs]
-#define RT R[insn.rtype.rt]
-#define RD R[insn.rtype.rd]
+#define RA R[insn.rtype.ra]
+#define RB R[insn.rtype.rb]
+#define RC R[insn.rtype.rc]
+#define BIGIMM insn.btype.bigimm
 #define IMM insn.itype.imm
-#define SIMM ((int16_t)insn.itype.imm)
+#define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 #define SHAMT insn.rtype.shamt
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (SIMM*sizeof(insn_t)))
-#define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)-1)) + TARGET*sizeof(insn_t))
+#define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)*sizeof(insn_t)-1)) + TARGET*sizeof(insn_t))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction
diff --git a/riscv/execute.h b/riscv/execute.h
index 66ce0e0..54bf52d 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -1,635 +1,1147 @@
 /* Automatically generated by parse-opcodes */
-switch(opcode)
+switch((insn.bits >> 0x19) & 0x7f)
 {
-  case 0:
+  case 0x0:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
-      {
-        case 0:
-          {
-            #include "insns/unimp.h"
-          }
-          break;
-        case 1:
-          {
-            #include "insns/sll.h"
-          }
-          break;
-        case 2:
-          {
-            #include "insns/srl.h"
-          }
-          break;
-        case 3:
-          {
-            #include "insns/sra.h"
-          }
-          break;
-        case 5:
-          {
-            #include "insns/sllv.h"
-          }
-          break;
-        case 6:
-          {
-            #include "insns/srlv.h"
-          }
-          break;
-        case 7:
-          {
-            #include "insns/srav.h"
-          }
-          break;
-        case 9:
-          {
-            #include "insns/jalr.h"
-          }
-          break;
-        case 10:
-          {
-            #include "insns/movz.h"
-          }
-          break;
-        case 11:
-          {
-            #include "insns/movn.h"
-          }
-          break;
-        case 12:
-          {
-            #include "insns/syscall.h"
-          }
-          break;
-        case 13:
-          {
-            #include "insns/break.h"
-          }
-          break;
-        case 14:
-          {
-            #include "insns/rdhwr.h"
-          }
-          break;
-        case 15:
-          {
-            #include "insns/sync.h"
-          }
-          break;
-        case 17:
-          {
-            #include "insns/dsll.h"
-          }
-          break;
-        case 18:
-          {
-            #include "insns/dsrl.h"
-          }
-          break;
-        case 19:
-          {
-            #include "insns/dsra.h"
-          }
-          break;
-        case 21:
-          {
-            #include "insns/dsllv.h"
-          }
-          break;
-        case 22:
-          {
-            #include "insns/dsrlv.h"
-          }
-          break;
-        case 23:
-          {
-            #include "insns/dsrav.h"
-          }
-          break;
-        case 25:
-          {
-            #include "insns/dsll32.h"
-          }
-          break;
-        case 26:
-          {
-            #include "insns/dsrl32.h"
-          }
-          break;
-        case 27:
-          {
-            #include "insns/dsra32.h"
-          }
-          break;
-        case 32:
-          {
-            #include "insns/add.h"
-          }
-          break;
-        case 33:
-          {
-            #include "insns/sub.h"
-          }
-          break;
-        case 34:
-          {
-            #include "insns/slt.h"
-          }
-          break;
-        case 35:
-          {
-            #include "insns/sltu.h"
-          }
-          break;
-        case 36:
-          {
-            #include "insns/and.h"
-          }
-          break;
-        case 37:
-          {
-            #include "insns/or.h"
-          }
-          break;
-        case 38:
-          {
-            #include "insns/xor.h"
-          }
-          break;
-        case 39:
-          {
-            #include "insns/nor.h"
-          }
-          break;
-        case 40:
-          {
-            #include "insns/mul.h"
-          }
-          break;
-        case 48:
-          {
-            #include "insns/dadd.h"
-          }
-          break;
-        case 49:
-          {
-            #include "insns/dsub.h"
-          }
-          break;
-        case 56:
-          {
-            #include "insns/dmul.h"
-          }
-          break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+      case 0x0:
+      {
+        if((insn.bits & 0xffffffff) == 0x0)
+        {
+          #include "insns/unimp.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 1:
-    {
-      #include "insns/synci.h"
-    }
-    break;
-  case 2:
-    {
-      #include "insns/j.h"
-    }
-    break;
-  case 3:
-    {
-      #include "insns/jal.h"
-    }
-    break;
-  case 4:
-    {
-      #include "insns/beq.h"
-    }
-    break;
-  case 5:
-    {
-      #include "insns/bne.h"
-    }
+  }
+  case 0x60:
+  {
+    #include "insns/j.h"
     break;
-  case 8:
-    {
-      #include "insns/addi.h"
-    }
+  }
+  case 0x61:
+  {
+    #include "insns/j.h"
     break;
-  case 10:
-    {
-      #include "insns/slti.h"
-    }
+  }
+  case 0x62:
+  {
+    #include "insns/j.h"
     break;
-  case 11:
-    {
-      #include "insns/sltiu.h"
-    }
+  }
+  case 0x63:
+  {
+    #include "insns/j.h"
     break;
-  case 12:
-    {
-      #include "insns/andi.h"
-    }
+  }
+  case 0x64:
+  {
+    #include "insns/jal.h"
     break;
-  case 13:
-    {
-      #include "insns/ori.h"
-    }
+  }
+  case 0x65:
+  {
+    #include "insns/jal.h"
     break;
-  case 14:
-    {
-      #include "insns/xori.h"
-    }
+  }
+  case 0x66:
+  {
+    #include "insns/jal.h"
     break;
-  case 15:
-    {
-      #include "insns/lui.h"
-    }
+  }
+  case 0x67:
+  {
+    #include "insns/jal.h"
     break;
-  case 16:
+  }
+  case 0x68:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
+      case 0x0:
       {
-        case 0:
-          {
-            #include "insns/ei.h"
-          }
+        if((insn.bits & 0xfe007c00) == 0xd0000000)
+        {
+          #include "insns/add_fmt.h"
           break;
-        case 1:
-          {
-            #include "insns/di.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0001000)
+        {
+          #include "insns/sub_fmt.h"
           break;
-        case 2:
-          {
-            #include "insns/eret.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0002000)
+        {
+          #include "insns/mul_fmt.h"
           break;
-        case 24:
-          {
-            #include "insns/mfc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0003000)
+        {
+          #include "insns/div_fmt.h"
           break;
-        case 25:
-          {
-            #include "insns/dmfc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0004000)
+        {
+          #include "insns/sqrt_fmt.h"
           break;
-        case 28:
-          {
-            #include "insns/mtc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0005000)
+        {
+          #include "insns/abs_fmt.h"
           break;
-        case 29:
-          {
-            #include "insns/dmtc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0006000)
+        {
+          #include "insns/mov_fmt.h"
           break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0007000)
+        {
+          #include "insns/neg_fmt.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 17:
+  }
+  case 0x69:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
-      {
-        case 0:
-          {
-            #include "insns/add_fmt.h"
-          }
-          break;
-        case 1:
-          {
-            #include "insns/sub_fmt.h"
-          }
-          break;
-        case 2:
-          {
-            #include "insns/mul_fmt.h"
-          }
-          break;
-        case 3:
-          {
-            #include "insns/div_fmt.h"
-          }
-          break;
-        case 4:
-          {
-            #include "insns/sqrt_fmt.h"
-          }
-          break;
-        case 5:
-          {
-            #include "insns/abs_fmt.h"
-          }
-          break;
-        case 6:
-          {
-            #include "insns/mov_fmt.h"
-          }
-          break;
-        case 7:
-          {
-            #include "insns/neg_fmt.h"
-          }
-          break;
-        case 8:
-          {
-            #include "insns/round_l_fmt.h"
-          }
-          break;
-        case 9:
-          {
-            #include "insns/trunc_l_fmt.h"
-          }
-          break;
-        case 10:
-          {
-            #include "insns/ceil_l_fmt.h"
-          }
-          break;
-        case 11:
-          {
-            #include "insns/floor_l_fmt.h"
-          }
-          break;
-        case 12:
-          {
-            #include "insns/round_w_fmt.h"
-          }
-          break;
-        case 13:
-          {
-            #include "insns/trunc_w_fmt.h"
-          }
-          break;
-        case 14:
-          {
-            #include "insns/ceil_w_fmt.h"
-          }
-          break;
-        case 15:
-          {
-            #include "insns/floor_w_fmt.h"
-          }
-          break;
-        case 24:
-          {
-            #include "insns/mfc1.h"
-          }
-          break;
-        case 25:
-          {
-            #include "insns/dmfc1.h"
-          }
-          break;
-        case 26:
-          {
-            #include "insns/cfc1.h"
-          }
-          break;
-        case 27:
-          {
-            #include "insns/mfhc1.h"
-          }
-          break;
-        case 28:
-          {
-            #include "insns/mtc1.h"
-          }
-          break;
-        case 29:
-          {
-            #include "insns/dmtc1.h"
-          }
-          break;
-        case 30:
-          {
-            #include "insns/ctc1.h"
-          }
-          break;
-        case 31:
-          {
-            #include "insns/mthc1.h"
-          }
-          break;
-        case 32:
-          {
-            #include "insns/cvt_s_fmt.h"
-          }
-          break;
-        case 33:
-          {
-            #include "insns/cvt_d_fmt.h"
-          }
-          break;
-        case 36:
-          {
-            #include "insns/cvt_w_fmt.h"
-          }
-          break;
-        case 37:
-          {
-            #include "insns/cvt_l_fmt.h"
-          }
-          break;
-        case 48:
-          {
-            #include "insns/c_f_fmt.h"
-          }
-          break;
-        case 49:
-          {
-            #include "insns/c_un_fmt.h"
-          }
-          break;
-        case 50:
-          {
-            #include "insns/c_eq_fmt.h"
-          }
-          break;
-        case 51:
-          {
-            #include "insns/c_ueq_fmt.h"
-          }
-          break;
-        case 52:
-          {
-            #include "insns/c_olt_fmt.h"
-          }
-          break;
-        case 53:
-          {
-            #include "insns/c_ult_fmt.h"
-          }
-          break;
-        case 54:
-          {
-            #include "insns/c_ole_fmt.h"
-          }
-          break;
-        case 55:
-          {
-            #include "insns/c_ule_fmt.h"
-          }
-          break;
-        case 56:
-          {
-            #include "insns/c_sf_fmt.h"
-          }
-          break;
-        case 57:
-          {
-            #include "insns/c_ngle_fmt.h"
-          }
-          break;
-        case 58:
-          {
-            #include "insns/c_seq_fmt.h"
-          }
-          break;
-        case 59:
-          {
-            #include "insns/c_ngl_fmt.h"
-          }
-          break;
-        case 60:
-          {
-            #include "insns/c_lt_fmt.h"
-          }
-          break;
-        case 61:
-          {
-            #include "insns/c_nge_fmt.h"
-          }
-          break;
-        case 62:
-          {
-            #include "insns/c_le_fmt.h"
-          }
-          break;
-        case 63:
-          {
-            #include "insns/c_ngt_fmt.h"
-          }
-          break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2000000)
+        {
+          #include "insns/round_l_fmt.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2001000)
+        {
+          #include "insns/trunc_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2002000)
+        {
+          #include "insns/ceil_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2003000)
+        {
+          #include "insns/floor_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2004000)
+        {
+          #include "insns/round_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2005000)
+        {
+          #include "insns/trunc_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2006000)
+        {
+          #include "insns/ceil_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2007000)
+        {
+          #include "insns/floor_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 20:
-    {
-      #include "insns/blt.h"
-    }
-    break;
-  case 21:
-    {
-      #include "insns/bltu.h"
-    }
-    break;
-  case 22:
-    {
-      #include "insns/ble.h"
-    }
-    break;
-  case 23:
-    {
-      #include "insns/bleu.h"
-    }
-    break;
-  case 24:
-    {
-      #include "insns/daddi.h"
-    }
-    break;
-  case 32:
-    {
-      #include "insns/lb.h"
-    }
-    break;
-  case 33:
+  }
+  case 0x6a:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lh.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4000000)
+        {
+          #include "insns/mfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4001000)
+        {
+          #include "insns/dmfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4002000)
+        {
+          #include "insns/cfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4003000)
+        {
+          #include "insns/mfhc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4004000)
+        {
+          #include "insns/mtc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4005000)
+        {
+          #include "insns/dmtc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4006000)
+        {
+          #include "insns/ctc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4007000)
+        {
+          #include "insns/mthc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 35:
+  }
+  case 0x6b:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lw.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6000000)
+        {
+          #include "insns/cvt_s_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6001000)
+        {
+          #include "insns/cvt_d_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6004000)
+        {
+          #include "insns/cvt_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6005000)
+        {
+          #include "insns/cvt_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 36:
+  }
+  case 0x6c:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lbu.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8000000)
+        {
+          #include "insns/c_f_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8001000)
+        {
+          #include "insns/c_un_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8002000)
+        {
+          #include "insns/c_eq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8003000)
+        {
+          #include "insns/c_ueq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8004000)
+        {
+          #include "insns/c_olt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8005000)
+        {
+          #include "insns/c_ult_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8006000)
+        {
+          #include "insns/c_ole_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8007000)
+        {
+          #include "insns/c_ule_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 37:
+  }
+  case 0x6d:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lhu.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda000000)
+        {
+          #include "insns/c_sf_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda001000)
+        {
+          #include "insns/c_ngle_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda002000)
+        {
+          #include "insns/c_seq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda003000)
+        {
+          #include "insns/c_ngl_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda004000)
+        {
+          #include "insns/c_lt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda005000)
+        {
+          #include "insns/c_nge_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda006000)
+        {
+          #include "insns/c_le_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda007000)
+        {
+          #include "insns/c_ngt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 39:
-    {
-      #include "insns/lwu.h"
-    }
+  }
+  case 0x71:
+  {
+    #include "insns/lui.h"
     break;
-  case 40:
-    {
-      #include "insns/sb.h"
-    }
+  }
+  case 0x72:
+  {
+    #include "insns/slori.h"
     break;
-  case 41:
+  }
+  case 0x73:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sh.h"
+      case 0x0:
+      {
+        #include "insns/beq.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/bne.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/blt.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/bltu.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/ble.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/bleu.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 43:
+  }
+  case 0x74:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sw.h"
+      case 0x0:
+      {
+        #include "insns/addi.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/daddi.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/slti.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/sltiu.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/andi.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/ori.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/xori.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 49:
+  }
+  case 0x75:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/l_s.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
+        {
+          #include "insns/nor.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000060)
+        {
+          #include "insns/sltu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0000c0)
+        {
+          #include "insns/xor.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000020)
+        {
+          #include "insns/sub.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0000a0)
+        {
+          #include "insns/or.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000000)
+        {
+          #include "insns/add.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000040)
+        {
+          #include "insns/slt.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000080)
+        {
+          #include "insns/and.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea001000)
+        {
+          #include "insns/mul.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001080)
+        {
+          #include "insns/div.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010c0)
+        {
+          #include "insns/rem.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001040)
+        {
+          #include "insns/mulh.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010e0)
+        {
+          #include "insns/remu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001060)
+        {
+          #include "insns/mulhu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010a0)
+        {
+          #include "insns/divu.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea004040)
+        {
+          #include "insns/srlv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea004020)
+        {
+          #include "insns/sllv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea004060)
+        {
+          #include "insns/srav.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea005000)
+        {
+          #include "insns/sll.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea006000)
+        {
+          #include "insns/srl.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea007000)
+        {
+          #include "insns/sra.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 53:
+  }
+  case 0x76:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/l_d.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec000020)
+        {
+          #include "insns/dsub.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec000000)
+        {
+          #include "insns/dadd.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec0010e0)
+        {
+          #include "insns/dremu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001080)
+        {
+          #include "insns/ddiv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
+        {
+          #include "insns/drem.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001060)
+        {
+          #include "insns/dmulhu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001000)
+        {
+          #include "insns/dmul.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001040)
+        {
+          #include "insns/dmulh.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
+        {
+          #include "insns/ddivu.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec004020)
+        {
+          #include "insns/dsllv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec004060)
+        {
+          #include "insns/dsrav.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec004040)
+        {
+          #include "insns/dsrlv.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec005000)
+        {
+          #include "insns/dsll.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec005400)
+        {
+          #include "insns/dsll32.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec006400)
+        {
+          #include "insns/dsrl32.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec006000)
+        {
+          #include "insns/dsrl.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec007400)
+        {
+          #include "insns/dsra32.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec007000)
+        {
+          #include "insns/dsra.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 55:
+  }
+  case 0x78:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/ld.h"
+      case 0x0:
+      {
+        #include "insns/lb.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/lh.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/lw.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/ld.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/lbu.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/lhu.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/lwu.h"
+        break;
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07000) == 0xf0007000)
+        {
+          #include "insns/synci.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 57:
+  }
+  case 0x79:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/s_s.h"
+      case 0x0:
+      {
+        #include "insns/sb.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/sh.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/sw.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/sd.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/l_s.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/l_d.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/s_s.h"
+        break;
+      }
+      case 0x7:
+      {
+        #include "insns/s_d.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 61:
+  }
+  case 0x7b:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/s_d.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0fffe0) == 0xf6000000)
+        {
+          #include "insns/jalr_c.h"
+          break;
+        }
+        if((insn.bits & 0xfe0fffe0) == 0xf6000040)
+        {
+          #include "insns/jalr_j.h"
+          break;
+        }
+        if((insn.bits & 0xfe0fffe0) == 0xf6000020)
+        {
+          #include "insns/jalr_r.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xffffffe0) == 0xf6001000)
+        {
+          #include "insns/rdpc.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        {
+          #include "insns/rdhwr.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6003000)
+        {
+          #include "insns/sync.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6004000)
+        {
+          #include "insns/syscall.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6005000)
+        {
+          #include "insns/break.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 63:
+  }
+  case 0x7e:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sd.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0fffff) == 0xfc000000)
+        {
+          #include "insns/ei.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0fffff) == 0xfc001000)
+        {
+          #include "insns/di.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xffffffff) == 0xfc002000)
+        {
+          #include "insns/eret.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc004000)
+        {
+          #include "insns/mfc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc005000)
+        {
+          #include "insns/dmfc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc006000)
+        {
+          #include "insns/mtc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc007000)
+        {
+          #include "insns/dmtc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
+  }
   default:
-    {
-      #include "insns/unimp.h"
-    }
-    break;
+  {
+    #include "insns/unimp.h"
   }
+}
diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index c50729f..bfbc485 100644
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
-RD = sext32(RS + RT);
+RC = sext32(RA + RB);
 
diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index c84299d..6935cca 100644
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RT = sext32(RS + SIMM);
+RA = sext32(SIMM + RB);
diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index b109b53..305e541 100644
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RD = RS & RT;
+RC = RA & RB;
diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 669b658..86a045c 100644
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RT = RS & IMM;
+RA = IMM & RB;
diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h
index 3ebde2f..320c33f 100644
--- a/riscv/insns/beq.h
+++ b/riscv/insns/beq.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) == cmp_trunc(RT))
+if(cmp_trunc(RA) == cmp_trunc(RB))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/ble.h b/riscv/insns/ble.h
index f5e2196..c8547bd 100644
--- a/riscv/insns/ble.h
+++ b/riscv/insns/ble.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS)) <= sreg_t(cmp_trunc(RT)))
+if(sreg_t(cmp_trunc(RA)) <= sreg_t(cmp_trunc(RB)))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/bleu.h b/riscv/insns/bleu.h
index c2c1139..8827d68 100644
--- a/riscv/insns/bleu.h
+++ b/riscv/insns/bleu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) <= cmp_trunc(RT))
+if(cmp_trunc(RA) <= cmp_trunc(RB))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index 1010133..8d95127 100644
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(RT)))
+if(sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB)))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index a911aea..27deefe 100644
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) < cmp_trunc(RT))
+if(cmp_trunc(RA) < cmp_trunc(RB))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h
index a97d81a..aee98f6 100644
--- a/riscv/insns/bne.h
+++ b/riscv/insns/bne.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) != cmp_trunc(RT))
+if(cmp_trunc(RA) != cmp_trunc(RB))
   npc = BRANCH_TARGET;
diff --git a/riscv/insns/dadd.h b/riscv/insns/dadd.h
index 13b42ce..746cd80 100644
--- a/riscv/insns/dadd.h
+++ b/riscv/insns/dadd.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS + RT;
+RC = RA + RB;
diff --git a/riscv/insns/daddi.h b/riscv/insns/daddi.h
index bd217a0..b6b208d 100644
--- a/riscv/insns/daddi.h
+++ b/riscv/insns/daddi.h
@@ -1,2 +1,2 @@
 require64;
-RT = RS + SIMM;
+RA = SIMM + RB;
diff --git a/riscv/insns/ddiv.h b/riscv/insns/ddiv.h
index 009997e..f0c2d2b 100644
--- a/riscv/insns/ddiv.h
+++ b/riscv/insns/ddiv.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RS) / sreg_t(RT);
+RC = sreg_t(RA) / sreg_t(RB);
diff --git a/riscv/insns/ddivu.h b/riscv/insns/ddivu.h
index 4034603..a4e3f4f 100644
--- a/riscv/insns/ddivu.h
+++ b/riscv/insns/ddivu.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS / RT;
+RC = RA / RB;
diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index 50bcda9..d3c70a9 100644
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RT = temp;
+RA = temp;
diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 5c02888..e595c85 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
-RD = sext32(int32_t(RS)/int32_t(RT));
+RC = sext32(int32_t(RA)/int32_t(RB));
 
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 9ccf018..68f96a5 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
-RD = sext32(uint32_t(RS)/uint32_t(RT));
+RC = sext32(uint32_t(RA)/uint32_t(RB));
 
diff --git a/riscv/insns/dmfc0.h b/riscv/insns/dmfc0.h
index b905d31..7808458 100644
--- a/riscv/insns/dmfc0.h
+++ b/riscv/insns/dmfc0.h
@@ -1,29 +1,29 @@
 require_supervisor;
 require64;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    RT = sr;
+    RA = sr;
     break;
   case 1:
-    RT = epc;
+    RA = epc;
     break;
   case 2:
-    RT = badvaddr;
+    RA = badvaddr;
     break;
   case 3:
-    RT = ebase;
+    RA = ebase;
     break;
 
   case 8:
-    RT = MEMSIZE >> 12;
+    RA = MEMSIZE >> 12;
     break;
 
   case 17:
-    RT = sim->get_fromhost();
+    RA = sim->get_fromhost();
     break;
 
   default:
-    RT = -1;
+    RA = -1;
 }
diff --git a/riscv/insns/dmtc0.h b/riscv/insns/dmtc0.h
index 3347605..67195a6 100644
--- a/riscv/insns/dmtc0.h
+++ b/riscv/insns/dmtc0.h
@@ -1,19 +1,19 @@
 require_supervisor;
 require64;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(RT);
+    set_sr(RA);
     break;
   case 1:
-    epc = RT;
+    epc = RA;
     break;
   case 3:
-    ebase = RT & ~0xFFF;
+    ebase = RA & ~0xFFF;
     break;
 
   case 16:
-    sim->set_tohost(RT);
+    sim->set_tohost(RA);
     break;
 }
diff --git a/riscv/insns/dmul.h b/riscv/insns/dmul.h
index 96c4128..9c81285 100644
--- a/riscv/insns/dmul.h
+++ b/riscv/insns/dmul.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS * RT;
+RC = RA * RB;
diff --git a/riscv/insns/dmulh.h b/riscv/insns/dmulh.h
new file mode 100644
index 0000000..2d7ca4c
--- /dev/null
+++ b/riscv/insns/dmulh.h
@@ -0,0 +1,4 @@
+require64;
+int64_t rb = RA;
+int64_t ra = RB;
+RC = (int128_t(rb) * int128_t(ra)) >> 64;
diff --git a/riscv/insns/dmulhu.h b/riscv/insns/dmulhu.h
new file mode 100644
index 0000000..45e9704
--- /dev/null
+++ b/riscv/insns/dmulhu.h
@@ -0,0 +1,2 @@
+require64;
+RC = (uint128_t(RA) * uint128_t(RB)) >> 64;
diff --git a/riscv/insns/drem.h b/riscv/insns/drem.h
new file mode 100644
index 0000000..dfece43
--- /dev/null
+++ b/riscv/insns/drem.h
@@ -0,0 +1,2 @@
+require64;
+RC = sreg_t(RA) % sreg_t(RB);
diff --git a/riscv/insns/dremu.h b/riscv/insns/dremu.h
new file mode 100644
index 0000000..e8ee6b1
--- /dev/null
+++ b/riscv/insns/dremu.h
@@ -0,0 +1,2 @@
+require64;
+RC = RA % RB;
diff --git a/riscv/insns/dsll.h b/riscv/insns/dsll.h
index 4051158..a07e038 100644
--- a/riscv/insns/dsll.h
+++ b/riscv/insns/dsll.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << SHAMT;
+RC = RB << SHAMT;
diff --git a/riscv/insns/dsll32.h b/riscv/insns/dsll32.h
index 679f0e2..cfd9ba3 100644
--- a/riscv/insns/dsll32.h
+++ b/riscv/insns/dsll32.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << (32+SHAMT);
+RC = RB << (32+SHAMT);
diff --git a/riscv/insns/dsllv.h b/riscv/insns/dsllv.h
index 828e767..7e81e6b 100644
--- a/riscv/insns/dsllv.h
+++ b/riscv/insns/dsllv.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << (RS & 0x3F);
+RC = RB << (RA & 0x3F);
diff --git a/riscv/insns/dsra.h b/riscv/insns/dsra.h
index 60f9ad3..19118f0 100644
--- a/riscv/insns/dsra.h
+++ b/riscv/insns/dsra.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RT) >> SHAMT;
+RC = sreg_t(RB) >> SHAMT;
diff --git a/riscv/insns/dsra32.h b/riscv/insns/dsra32.h
index 0a5907f..001e3bd 100644
--- a/riscv/insns/dsra32.h
+++ b/riscv/insns/dsra32.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RT) >> (32+SHAMT);
+RC = sreg_t(RB) >> (32+SHAMT);
diff --git a/riscv/insns/dsrav.h b/riscv/insns/dsrav.h
index 27dba05..ec6fee8 100644
--- a/riscv/insns/dsrav.h
+++ b/riscv/insns/dsrav.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (RS & 0x3F);
+RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/dsrl.h b/riscv/insns/dsrl.h
index efc69e1..47426b1 100644
--- a/riscv/insns/dsrl.h
+++ b/riscv/insns/dsrl.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> SHAMT;
+RC = RB >> SHAMT;
diff --git a/riscv/insns/dsrl32.h b/riscv/insns/dsrl32.h
index f1bc91e..5d52dea 100644
--- a/riscv/insns/dsrl32.h
+++ b/riscv/insns/dsrl32.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (32+SHAMT);
+RC = RB >> (32+SHAMT);
diff --git a/riscv/insns/dsrlv.h b/riscv/insns/dsrlv.h
index 27dba05..ec6fee8 100644
--- a/riscv/insns/dsrlv.h
+++ b/riscv/insns/dsrlv.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (RS & 0x3F);
+RC = RB >> (RA & 0x3F);
diff --git a/riscv/insns/dsub.h b/riscv/insns/dsub.h
index 1c6f1c0..e7ac407 100644
--- a/riscv/insns/dsub.h
+++ b/riscv/insns/dsub.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS - RT;
+RC = RA - RB;
diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index 6d13be0..ca3586f 100644
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RT = temp;
+RA = temp;
diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
new file mode 100644
index 0000000..18b2508
--- /dev/null
+++ b/riscv/insns/jalr_c.h
@@ -0,0 +1,3 @@
+uint32_t temp = npc;
+npc = RA;
+RC = temp;
diff --git a/riscv/insns/jalr_j.h b/riscv/insns/jalr_j.h
new file mode 100644
index 0000000..5e9bb49
--- /dev/null
+++ b/riscv/insns/jalr_j.h
@@ -0,0 +1 @@
+#include "jalr_c.h"
diff --git a/riscv/insns/jalr_r.h b/riscv/insns/jalr_r.h
new file mode 100644
index 0000000..5e9bb49
--- /dev/null
+++ b/riscv/insns/jalr_r.h
@@ -0,0 +1 @@
+#include "jalr_c.h"
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index ed1c100..ac8bf64 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RT = mmu.load_int8(RS+SIMM);
+RA = mmu.load_int8(RB+SIMM);
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 020fd19..522eb8f 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RT = mmu.load_uint8(RS+SIMM);
+RA = mmu.load_uint8(RB+SIMM);
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 45bbcc2..241af6a 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RT = mmu.load_int64(RS+SIMM);
+RA = mmu.load_int64(RB+SIMM);
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index f0ef500..e46ee14 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RT = mmu.load_int16(RS+SIMM);
+RA = mmu.load_int16(RB+SIMM);
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 6d77f04..1f22423 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RT = mmu.load_uint16(RS+SIMM);
+RA = mmu.load_uint16(RB+SIMM);
diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 0be0c9b..0eb14bc 100644
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RT = IMM << 16;
+RA = sext32(BIGIMM << IMM_BITS);
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 123b4a8..e1f56fe 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RT = mmu.load_int32(RS+SIMM);
+RA = mmu.load_int32(RB+SIMM);
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index af7dfc9..311292d 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RT = mmu.load_uint32(RS+SIMM);
+RA = mmu.load_uint32(RB+SIMM);
diff --git a/riscv/insns/mfc0.h b/riscv/insns/mfc0.h
index f57539a..8a0a84a 100644
--- a/riscv/insns/mfc0.h
+++ b/riscv/insns/mfc0.h
@@ -1,28 +1,28 @@
 require_supervisor;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    RT = sext32(sr);
+    RA = sext32(sr);
     break;
   case 1:
-    RT = sext32(epc);
+    RA = sext32(epc);
     break;
   case 2:
-    RT = sext32(badvaddr);
+    RA = sext32(badvaddr);
     break;
   case 3:
-    RT = sext32(ebase);
+    RA = sext32(ebase);
     break;
 
   case 8:
-    RT = sext32(MEMSIZE >> 12);
+    RA = sext32(MEMSIZE >> 12);
     break;
 
   case 17:
-    RT = sext32(sim->get_fromhost());
+    RA = sext32(sim->get_fromhost());
     break;
 
   default:
-    RT = -1;
+    RA = -1;
 }
diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h
index 8688b0e..bdf6e5f 100644
--- a/riscv/insns/movn.h
+++ b/riscv/insns/movn.h
@@ -1 +1 @@
-if(RT) RD = RS;
+if(RB) RC = RA;
diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h
index 35bf498..45f4f07 100644
--- a/riscv/insns/movz.h
+++ b/riscv/insns/movz.h
@@ -1 +1 @@
-if(!RT) RD = RS;
+if(!RB) RC = RA;
diff --git a/riscv/insns/mtc0.h b/riscv/insns/mtc0.h
index d45d459..ca593df 100644
--- a/riscv/insns/mtc0.h
+++ b/riscv/insns/mtc0.h
@@ -1,18 +1,18 @@
 require_supervisor;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(sext32(RT));
+    set_sr(sext32(RA));
     break;
   case 1:
-    epc = sext32(RT);
+    epc = sext32(RA);
     break;
   case 3:
-    ebase = sext32(RT & ~0xFFF);
+    ebase = sext32(RA & ~0xFFF);
     break;
 
   case 16:
-    sim->set_tohost(sext32(RT));
+    sim->set_tohost(sext32(RA));
     break;
 }
diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 3a8fa69..d999172 100644
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
-RD = sext32(RS * RT);
+RC = sext32(RA * RB);
 
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
new file mode 100644
index 0000000..90a17be
--- /dev/null
+++ b/riscv/insns/mulh.h
@@ -0,0 +1,2 @@
+RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
new file mode 100644
index 0000000..9f3de3f
--- /dev/null
+++ b/riscv/insns/mulhu.h
@@ -0,0 +1,2 @@
+RC = sext32((RA * RB) >> 32);
+
diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index 1e8fa52..5bb7e89 100644
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RD = ~(RS | RT);
+RC = ~(RA | RB);
diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index daee005..d88c9f8 100644
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RD = RS | RT;
+RC = RA | RB;
diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index cfcf9e0..2fab937 100644
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RT = RS | IMM;
+RA = IMM | RB;
diff --git a/riscv/insns/rdpc.h b/riscv/insns/rdpc.h
new file mode 100644
index 0000000..95e528a
--- /dev/null
+++ b/riscv/insns/rdpc.h
@@ -0,0 +1 @@
+RC = npc;
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
new file mode 100644
index 0000000..1bb3051
--- /dev/null
+++ b/riscv/insns/rem.h
@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA) % int32_t(RB));
+
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
new file mode 100644
index 0000000..d028488
--- /dev/null
+++ b/riscv/insns/remu.h
@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA) % uint32_t(RB));
+
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index f70b2ef..618140d 100644
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS+SIMM, RT);
+mmu.store_uint8(RB+SIMM, RA);
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 03e6416..6a698ee 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RS+SIMM, RT);
+mmu.store_uint64(RB+SIMM, RA);
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index 72e24cc..e0fdc0a 100644
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RS+SIMM, RT);
+mmu.store_uint16(RB+SIMM, RA);
diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index fe32e89..67e6809 100644
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1 @@
-RD = sext32(RT << SHAMT);
+RC = sext32(RB << SHAMT);
diff --git a/riscv/insns/sllv.h b/riscv/insns/sllv.h
index eab1652..f694a2f 100644
--- a/riscv/insns/sllv.h
+++ b/riscv/insns/sllv.h
@@ -1 +1 @@
-RD = sext32(RT << (RS & 0x1F));
+RC = sext32(RB << (RA & 0x1F));
diff --git a/riscv/insns/slori.h b/riscv/insns/slori.h
new file mode 100644
index 0000000..732091b
--- /dev/null
+++ b/riscv/insns/slori.h
@@ -0,0 +1 @@
+RA = (RA << 32) | (BIGIMM << IMM_BITS);
diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 62f8684..ccc1d44 100644
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(RT));
+RC = sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB));
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 6de88a5..a5ef31e 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RT = sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(SIMM));
+RA = sreg_t(cmp_trunc(RB)) < sreg_t(cmp_trunc(SIMM));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 3b6390f..a09f3ec 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RT = cmp_trunc(RS) < cmp_trunc(SIMM);
+RA = cmp_trunc(RB) < cmp_trunc(SIMM);
diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 6687316..32fc94d 100644
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS) < cmp_trunc(RT);
+RC = cmp_trunc(RA) < cmp_trunc(RB);
diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index ef43a4e..c2decb9 100644
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RD = sext32(sreg_t(RT) >> SHAMT);
+RC = sext32(sreg_t(RB) >> SHAMT);
diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h
index a07fc56..8e9aa88 100644
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@@ -1 +1 @@
-RD = sext32(sreg_t(RT) >> (RS & 0x1F));
+RC = sext32(sreg_t(RB) >> (RA & 0x1F));
diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 9895896..0537a1c 100644
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1 +1 @@
-RD = sext32(RT >> SHAMT);
+RC = sext32(RB >> SHAMT);
diff --git a/riscv/insns/srlv.h b/riscv/insns/srlv.h
index 931d43a..7e1755f 100644
--- a/riscv/insns/srlv.h
+++ b/riscv/insns/srlv.h
@@ -1 +1 @@
-RD = sext32(RT >> (RS & 0x1F));
+RC = sext32(RB >> (RA & 0x1F));
diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 0618fb8..60bcf27 100644
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
-RD = sext32(RS - RT);
+RC = sext32(RA - RB);
 
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 7e9fff8..b4e3b3d 100644
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(RS+SIMM, RT);
+mmu.store_uint32(RB+SIMM, RA);
diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 66896f4..9d02447 100644
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RD = RS ^ RT;
+RC = RA ^ RB;
diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 4814c5b..5ca4637 100644
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RT = RS ^ IMM;
+RA = IMM ^ RB;
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 46ddd3b..eea26bb 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -4,7 +4,7 @@
 class mmu_t
 {
 public:
-  mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz) {}
+  mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz), badvaddr(0) {}
 
   #define load_func(type) \
     type##_t load_##type(reg_t addr) { \
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 23761d3..ad8ee67 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -18,6 +18,9 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   set_sr(SR_S);
 
   memset(counters,0,sizeof(counters));
+
+  static_assert(sizeof(insn_t) == 4);
+  static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
 }
 
 void processor_t::init(uint32_t _id)
@@ -45,8 +48,6 @@ void processor_t::step(size_t n, bool noisy)
     {
       insn_t insn = mmu.load_insn(pc);
   
-      int opcode = insn.rtype.opcode;
-      int funct = insn.rtype.funct;
       reg_t npc = pc+sizeof(insn);
 
       if(noisy)
-- 
2.30.2