From e81b0060b849373bd2afe04896bde505bfbd4425 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 16:51:22 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5ded5ded2..47556095e 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -81,7 +81,8 @@ behaviour*)
 In Vertical-First Mode, the `ALL` bit still applies, but to the elements
 that are executed up to the Hint length, in parallel batches. Contrast
 this with Horizontal-First Mode which tests elements from
-`0..VL-1`, Vertical-First tests elements `srcstep..MIN(srcstep+VFHint,VL-1)` See
+`0..VL-1`, Vertical-First tests elements
+`srcstep..MIN(srcstep+VFHint-1,VL-1)`. See
 [[sv/setvl]] for the definition of Vertical-First Hint.
 
 Predication in both INT and CR modes may be applied to `sv.bc` and other
-- 
2.30.2