From e82512b53f95fb126ad5f06b7b97833d66858e77 Mon Sep 17 00:00:00 2001
From: Luke Leighton <lkcl@lkcl.net>
Date: Tue, 27 Feb 2018 00:21:20 +0000
Subject: [PATCH] add more interfaces

---
 shakti/m_class.mdwn          | 6 ++++++
 shakti/m_class/AXI.mdwn      | 6 ++++++
 shakti/m_class/wishbone.mdwn | 6 ++++++
 3 files changed, 18 insertions(+)
 create mode 100644 shakti/m_class/AXI.mdwn
 create mode 100644 shakti/m_class/wishbone.mdwn

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 4c69326e6..6c4980498 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -220,6 +220,12 @@ List of Interfaces:
 * [[SPI]]
 * SD/MMC and eMMC [[sdmmc]]
 * Pin Multiplexing [[pinmux]]
+* Gigabit Ethernet [[RGMII]]
+
+List of Internal Interfaces:
+
+* [[AXI]]
+* [[wishbone]]
 
 # Items requiring clarification, or proposals TBD
 
diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
new file mode 100644
index 000000000..534538bda
--- /dev/null
+++ b/shakti/m_class/AXI.mdwn
@@ -0,0 +1,6 @@
+# AXI Bridge
+
+See also [[wishbone]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-axis>
diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
new file mode 100644
index 000000000..8606bac42
--- /dev/null
+++ b/shakti/m_class/wishbone.mdwn
@@ -0,0 +1,6 @@
+# Wishbone Bridge
+
+See also [[AXI]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-wishbone>
-- 
2.30.2