From e8382995b860b6949c075ceb063f2a1bd942bd9b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 8 Sep 2020 09:06:11 +0100 Subject: [PATCH] add cxxsim option --- src/soc/simple/test/test_issuer.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 91e68a71..6426d05b 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -5,7 +5,10 @@ related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=363 """ from nmigen import Module, Signal, Cat -from nmigen.back.pysim import Simulator, Delay, Settle +if True: + from nmigen.back.pysim import Simulator, Delay, Settle +else: + from nmigen.sim.cxxsim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -- 2.30.2