From e838e0e9cb239564370a3ee7cb8df5cb8fc33e2e Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 21 Oct 2022 16:37:14 -0700 Subject: [PATCH] format code removing unused imports --- src/openpower/decoder/isa/caller.py | 119 ++-- src/openpower/decoder/isa/test_caller.py | 23 +- src/openpower/decoder/isa/test_caller_alu.py | 3 +- src/openpower/decoder/isa/test_caller_bcd.py | 10 +- .../decoder/isa/test_caller_bcd_full.py | 13 +- .../decoder/isa/test_caller_bigint.py | 3 +- .../decoder/isa/test_caller_bitmanip.py | 3 +- .../decoder/isa/test_caller_bitmanip_av.py | 3 +- src/openpower/decoder/isa/test_caller_exts.py | 20 +- .../decoder/isa/test_caller_fmvis.py | 3 +- src/openpower/decoder/isa/test_caller_fp.py | 132 ++-- .../decoder/isa/test_caller_fptrans.py | 3 +- .../isa/test_caller_ldst_exceptions.py | 34 +- .../decoder/isa/test_caller_logical.py | 3 +- src/openpower/decoder/isa/test_caller_mul.py | 3 +- .../decoder/isa/test_caller_prefix_codes.py | 3 +- .../decoder/isa/test_caller_radix.py | 112 ++-- .../decoder/isa/test_caller_setvl.py | 624 +++++++++--------- .../decoder/isa/test_caller_shift_rot.py | 1 + .../decoder/isa/test_caller_svindex.py | 368 +++++------ .../decoder/isa/test_caller_svp64.py | 88 ++- .../decoder/isa/test_caller_svp64_alu.py | 3 +- .../decoder/isa/test_caller_svp64_bc.py | 179 +++-- .../decoder/isa/test_caller_svp64_bigint.py | 3 +- .../decoder/isa/test_caller_svp64_chacha20.py | 114 ++-- .../decoder/isa/test_caller_svp64_dct.py | 507 +++++++------- .../isa/test_caller_svp64_dd_ffirst.py | 84 ++- .../decoder/isa/test_caller_svp64_elwidth.py | 3 +- .../decoder/isa/test_caller_svp64_fft.py | 378 +++++------ .../decoder/isa/test_caller_svp64_fp.py | 100 ++- .../decoder/isa/test_caller_svp64_fptrans.py | 3 +- .../decoder/isa/test_caller_svp64_inssort.py | 130 ++-- .../decoder/isa/test_caller_svp64_ldst.py | 217 +++--- .../decoder/isa/test_caller_svp64_logical.py | 3 +- .../isa/test_caller_svp64_mapreduce.py | 95 ++- .../decoder/isa/test_caller_svp64_matrix.py | 179 +++-- .../decoder/isa/test_caller_svp64_pack.py | 146 ++-- .../isa/test_caller_svp64_parallel_reduce.py | 92 ++- .../isa/test_caller_svp64_predication.py | 84 ++- .../decoder/isa/test_caller_svp64_subvl.py | 39 +- .../isa/test_caller_svp64_utf_8_validation.py | 3 +- .../decoder/isa/test_caller_svshape2.py | 21 +- .../decoder/isa/test_caller_svstate.py | 59 +- .../isa/test_caller_transcendentals.py | 65 +- 44 files changed, 1959 insertions(+), 2119 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 23e5bc03..1aae2e60 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -13,48 +13,33 @@ related bugs: * https://bugs.libre-soc.org/show_bug.cgi?id=424 """ -import re -from nmigen.sim import Settle, Delay +from collections import namedtuple +from copy import deepcopy from functools import wraps -from copy import copy, deepcopy -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.selectable_int import ( - FieldSelectableInt, - SelectableInt, - selectconcat, -) -from openpower.decoder.power_insn import SVP64Instruction -from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits, - insns, MicrOp, - In1Sel, In2Sel, In3Sel, - OutSel, CRInSel, CROutSel, LDSTMode, - SVMode, - SVP64RMMode, SVP64PredMode, - SVP64PredInt, SVP64PredCR, - SVP64LDSTmode, FPTRANS_INSNS) - -from openpower.decoder.power_enums import SVPtype - -from openpower.decoder.helpers import (exts, gtu, ltu, undefined, - ISACallerHelper, ISAFPHelpers) -from openpower.consts import PIb, MSRb # big-endian (PowerISA versions) -from openpower.consts import (SVP64MODE, SVP64MODEb, - SVP64CROffs, - ) -from openpower.decoder.power_svp64 import SVP64RM, decode_extra +from nmigen.sim import Settle +from openpower.consts import (MSRb, PIb, # big-endian (PowerISA versions) + SVP64CROffs, SVP64MODEb) +from openpower.decoder.helpers import (ISACallerHelper, ISAFPHelpers, exts, + gtu, undefined) +from openpower.decoder.isa.mem import Mem, MemException from openpower.decoder.isa.radixmmu import RADIX -from openpower.decoder.isa.mem import Mem, swap_order, MemException from openpower.decoder.isa.svshape import SVSHAPE from openpower.decoder.isa.svstate import SVP64State - - +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.power_enums import (FPTRANS_INSNS, CRInSel, CROutSel, + In1Sel, In2Sel, In3Sel, LDSTMode, + MicrOp, OutSel, SVMode, + SVP64LDSTmode, SVP64PredCR, + SVP64PredInt, SVP64PredMode, + SVP64RMMode, SVPtype, XER_bits, + insns, spr_byname, spr_dict) +from openpower.decoder.power_insn import SVP64Instruction +from openpower.decoder.power_svp64 import SVP64RM, decode_extra +from openpower.decoder.selectable_int import (FieldSelectableInt, + SelectableInt, selectconcat) from openpower.util import LogKind, log -from collections import namedtuple -import math -import sys - instruction_info = namedtuple('instruction_info', 'func read_regs uninit_regs write_regs ' + 'special_regs op_fields form asmregs') @@ -110,7 +95,7 @@ def get_masked_reg(regs, base, offs, ew_bits): gpr_offs = offs // (64//ew_bits) gpr_col = offs % (64//ew_bits) # compute the mask based on ew_bits - mask = (1<> (gpr_col*elwidth) & ((1<> (gpr_col*elwidth) & ((1 << elwidth)-1) # finally, return a SelectableInt at the required elwidth log("GPR call", ridx, "isvec", is_vec, "offs", offs, - "elwid", elwidth, "offs/col", gpr_offs, gpr_col, "val", hex(val)) + "elwid", elwidth, "offs/col", gpr_offs, gpr_col, "val", hex(val)) return SelectableInt(val, elwidth) def set_form(self, form): @@ -189,7 +173,7 @@ class GPR(dict): gpr_offs = offs // (64//elwidth) gpr_col = offs % (64//elwidth) # compute the mask based on elwidth - mask = (1<>> lst = ["fadds 3, 1, 2", ] """ - lst = ["fadds 3, 1, 2", # -32.3 + 32.3 = 0 - ] + lst = ["fadds 3, 1, 2", # -32.3 + 32.3 = 0 + ] fprs = [0] * 32 fprs[1] = 0xC040266660000000 @@ -295,8 +287,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fsubs 3, 1, 2", ] """ - lst = ["fsubs 3, 1, 2", # 0 - -32.3 = 32.3 - ] + lst = ["fsubs 3, 1, 2", # 0 - -32.3 = 32.3 + ] fprs = [0] * 32 fprs[1] = 0x0 @@ -312,8 +304,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fadd 3, 1, 2", ] """ - lst = ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8 - ] + lst = ["fadd 3, 1, 2", # 7.0 + -9.8 = -2.8 + ] fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -329,9 +321,9 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmuls 3, 1, 2", ] """ - lst = ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6 - "fmuls 29,12,8", # test - ] + lst = ["fmuls 3, 1, 2", # 7.0 * -9.8 = -68.6 + "fmuls 29,12,8", # test + ] fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -347,8 +339,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmuls 3, 1, 2", ] """ - lst = ["fmuls 3, 1, 2", # - ] + lst = ["fmuls 3, 1, 2", + ] fprs = [0] * 32 fprs[1] = 0xbfb0ab5100000000 @@ -362,11 +354,11 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmuls 3, 1, 2", ] """ - lst = ["fmuls 3, 1, 2", # - ] + lst = ["fmuls 3, 1, 2", + ] fprs = [0] * 32 - fprs[1] = 0xbe724e2000000000 # negative number + fprs[1] = 0xbe724e2000000000 # negative number fprs[2] = 0x0 # times zero with Program(lst, bigendian=False) as program: @@ -378,8 +370,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmuls 3, 1, 2", ] """ - lst = ["fmuls 3, 1, 2", # - ] + lst = ["fmuls 3, 1, 2", + ] fprs = [0] * 32 fprs[1] = 0xbfb0ab5100000000 @@ -393,8 +385,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmul 3, 1, 2", ] """ - lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6 - ] + lst = ["fmul 3, 1, 2", # 7.0 * -9.8 = -68.6 + ] fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -410,8 +402,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmadds 3, 1, 2, 4", ] """ - lst = ["fmadds 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -66.6 - ] + lst = ["fmadds 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -66.6 + ] fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -426,8 +418,8 @@ class DecoderTestCase(FHDLTestCase): """>>> lst = ["fmsubs 3, 1, 2, 4", ] """ - lst = ["fmsubs 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -70.6 - ] + lst = ["fmsubs 3, 1, 2, 4", # 7.0 * -9.8 + 2 = -70.6 + ] fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -445,7 +437,7 @@ class DecoderTestCase(FHDLTestCase): """ lst = ["fcfids 1, 2", "fcfids 3, 4", - ] + ] fprs = [0] * 32 fprs[2] = 7 @@ -459,15 +451,15 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(4), SelectableInt(-32, 64)) def run_tst_program(self, prog, initial_regs=None, - initial_mem=None, - initial_fprs=None): + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs) - print ("GPRs") + initial_fprs=initial_fprs) + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_fptrans.py b/src/openpower/decoder/isa/test_caller_fptrans.py index 384571c3..8e5b0370 100644 --- a/src/openpower/decoder/isa/test_caller_fptrans.py +++ b/src/openpower/decoder/isa/test_caller_fptrans.py @@ -2,8 +2,9 @@ """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.fptrans.fptrans_cases import FPTransCases +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py index c9982365..fa375226 100644 --- a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py +++ b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py @@ -1,24 +1,23 @@ +import unittest + from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle +from nmigen.sim import Settle, Simulator from nmutil.formaltest import FHDLTestCase -import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, inject -from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA from openpower.consts import PIb +from openpower.decoder.isa.all import ISA +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2 +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program class Register: def __init__(self, num): self.num = num + def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, - initial_cr=0,mem=None): + initial_cr=0, mem=None): if initial_sprs is None: initial_sprs = {} m = Module() @@ -42,7 +41,6 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) - def process(): yield pdecode2.dec.bigendian.eq(0) # little / big? @@ -76,7 +74,7 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False, class DecoderTestCase(FHDLTestCase): def test_load_misalign(self): - lst = ["addi 2, 0, 0x0010", # get PC off of zero + lst = ["addi 2, 0, 0x0010", # get PC off of zero "ldx 3, 0, 1", ] initial_regs = [0] * 32 @@ -86,20 +84,20 @@ class DecoderTestCase(FHDLTestCase): initial_mem = {0x0000: (0x5432123412345678, 8), 0x0008: (0xabcdef0187654321, 8), 0x0020: (0x1828384822324252, 8), - } + } with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, initial_mem) self.assertEqual(sim.gpr(1), SelectableInt(all1s, 64)) self.assertEqual(sim.gpr(3), SelectableInt(0, 64)) - print ("DAR", hex(sim.spr['DAR'].value)) - print ("PC", hex(sim.pc.CIA.value)) + print("DAR", hex(sim.spr['DAR'].value)) + print("PC", hex(sim.pc.CIA.value)) # TODO get MSR, test that. # TODO, test rest of SRR1 equal to zero - self.assertEqual(sim.spr['SRR1'][PIb.PRIV], 0x1) # expect priv bit + self.assertEqual(sim.spr['SRR1'][PIb.PRIV], 0x1) # expect priv bit self.assertEqual(sim.spr['SRR0'], 0x4) # expect to be 2nd op self.assertEqual(sim.spr['DAR'], all1s) # expect failed LD addr - self.assertEqual(sim.pc.CIA.value, 0x600) # align exception + self.assertEqual(sim.pc.CIA.value, 0x600) # align exception def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None): simulator = run_tst(prog, initial_regs, mem=initial_mem) diff --git a/src/openpower/decoder/isa/test_caller_logical.py b/src/openpower/decoder/isa/test_caller_logical.py index 9293cd03..c0ebdacc 100644 --- a/src/openpower/decoder/isa/test_caller_logical.py +++ b/src/openpower/decoder/isa/test_caller_logical.py @@ -6,8 +6,9 @@ related bugs: """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.logical.logical_cases import LogicalTestCase +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_mul.py b/src/openpower/decoder/isa/test_caller_mul.py index eb1441f2..add1e6b5 100644 --- a/src/openpower/decoder/isa/test_caller_mul.py +++ b/src/openpower/decoder/isa/test_caller_mul.py @@ -6,8 +6,9 @@ related bugs: """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.mul.mul_cases import MulTestCases2Arg, SVP64MAdd +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_prefix_codes.py b/src/openpower/decoder/isa/test_caller_prefix_codes.py index 732df41c..e78cd880 100644 --- a/src/openpower/decoder/isa/test_caller_prefix_codes.py +++ b/src/openpower/decoder/isa/test_caller_prefix_codes.py @@ -2,8 +2,9 @@ """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.prefix_codes.prefix_codes_cases import PrefixCodesCases +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_radix.py b/src/openpower/decoder/isa/test_caller_radix.py index 29759b7b..c7a9e195 100644 --- a/src/openpower/decoder/isa/test_caller_radix.py +++ b/src/openpower/decoder/isa/test_caller_radix.py @@ -1,95 +1,89 @@ -from nmigen import Module, Signal #from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, inject, RADIX -from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import run_tst - from copy import deepcopy +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.test_caller import run_tst +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program + testmem = { - 0x10000: # PARTITION_TABLE_2 (not implemented yet) - # PATB_GR=1 PRTB=0x1000 PRTS=0xb - 0x800000000100000b, - - 0x30000: # RADIX_ROOT_PTE - # V = 1 L = 0 NLB = 0x400 NLS = 9 - 0x8000000000040009, - 0x40000: # RADIX_SECOND_LEVEL - # V = 1 L = 1 SW = 0 RPN = 0 - # R = 1 C = 1 ATT = 0 EAA 0x7 - 0xc000000000000187, - - 0x30800: # RADIX_ROOT_PTE + 8 - # V = 1 L = 0 NLB = 0x408 NLS = 9 - 0x8000000000040809, - 0x40800: # RADIX_SECOND_LEVEL - # V = 1 L = 1 SW = 0 RPN = 0 - # R = 1 C = 1 ATT = 0 EAA 0x7 - 0xc000000000000187, - - 0x1000000: # PROCESS_TABLE_3 - # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13 - 0x40000000000300ad, - 0x1000008: # PROCESS_TABLE_3 + 8 - # RTS1 = 0x2 RPDB = 0x308 RTS2 = 0x5 RPDS = 13 - 0x40000000000308ad, - } - -prtbl = 0x1000000 # matches PROCESS_TABLE_3 above + 0x10000: # PARTITION_TABLE_2 (not implemented yet) + # PATB_GR=1 PRTB=0x1000 PRTS=0xb + 0x800000000100000b, + + 0x30000: # RADIX_ROOT_PTE + # V = 1 L = 0 NLB = 0x400 NLS = 9 + 0x8000000000040009, + 0x40000: # RADIX_SECOND_LEVEL + # V = 1 L = 1 SW = 0 RPN = 0 + # R = 1 C = 1 ATT = 0 EAA 0x7 + 0xc000000000000187, + + 0x30800: # RADIX_ROOT_PTE + 8 + # V = 1 L = 0 NLB = 0x408 NLS = 9 + 0x8000000000040809, + 0x40800: # RADIX_SECOND_LEVEL + # V = 1 L = 1 SW = 0 RPN = 0 + # R = 1 C = 1 ATT = 0 EAA 0x7 + 0xc000000000000187, + + 0x1000000: # PROCESS_TABLE_3 + # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13 + 0x40000000000300ad, + 0x1000008: # PROCESS_TABLE_3 + 8 + # RTS1 = 0x2 RPDB = 0x308 RTS2 = 0x5 RPDS = 13 + 0x40000000000308ad, +} + +prtbl = 0x1000000 # matches PROCESS_TABLE_3 above + class DecoderTestCase(FHDLTestCase): def test_load(self): - lst = [ "lwz 3, 0(1)" + lst = ["lwz 3, 0(1)" ] sprs = {'DSISR': SelectableInt(0, 64), 'DAR': SelectableInt(0, 64), 'PIDR': SelectableInt(0, 64), 'PRTBL': SelectableInt(prtbl, 64) - } + } - initial_regs=[0] * 32 + initial_regs = [0] * 32 initial_regs[1] = 0x1000 initial_regs[2] = 0x1234 initial_mem = deepcopy(testmem) - initial_mem[0x1000] = 0x1337 # data to be read + initial_mem[0x1000] = 0x1337 # data to be read with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=initial_regs, - initial_mem=initial_mem, - initial_sprs=sprs) + initial_mem=initial_mem, + initial_sprs=sprs) self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64)) def test_load_pid_1(self): - lst = [ "lwz 3, 0(1)" + lst = ["lwz 3, 0(1)" ] sprs = {'DSISR': SelectableInt(0, 64), 'DAR': SelectableInt(0, 64), 'PIDR': SelectableInt(1, 64), 'PRTBL': SelectableInt(prtbl, 64) - } + } - initial_regs=[0] * 32 + initial_regs = [0] * 32 initial_regs[1] = 0x1000 initial_regs[2] = 0x1234 initial_mem = deepcopy(testmem) - initial_mem[0x1000] = 0x1337 # data to be read + initial_mem[0x1000] = 0x1337 # data to be read with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=initial_regs, - initial_mem=initial_mem, - initial_sprs=sprs) + initial_mem=initial_mem, + initial_sprs=sprs) self.assertEqual(sim.gpr(3), SelectableInt(0x1337, 64)) def test_load_store(self): @@ -103,27 +97,27 @@ class DecoderTestCase(FHDLTestCase): 'DAR': SelectableInt(0, 64), 'PIDR': SelectableInt(0, 64), 'PRTBL': SelectableInt(prtbl, 64) - } + } - initial_regs=[0] * 32 + initial_regs = [0] * 32 initial_regs[1] = 0x1000 initial_regs[2] = 0x1234 initial_mem = deepcopy(testmem) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=initial_regs, - initial_mem=initial_mem, - initial_sprs=sprs) + initial_mem=initial_mem, + initial_sprs=sprs) self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) def run_tst_program(self, prog, initial_regs=None, initial_mem=None, - initial_sprs=None): + initial_sprs=None): # DO NOT set complex arguments, it is a "singleton" pattern if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mmu=True, mem=initial_mem, - initial_sprs=initial_sprs) + initial_sprs=initial_sprs) simulator.gpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index 4ce50ccd..f5112338 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -1,24 +1,18 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import CRFields, SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy + class DecoderTestCase(FHDLTestCase): def _check_regs(self, sim, expected): - print ("GPR") + print("GPR") sim.gpr.dump() for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) @@ -31,17 +25,17 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # but, ha! r4 (RA) is zero. and Rc=1. therefore, CR0 should be set EQ svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 0) self.assertEqual(sim.svstate.maxvl, 5) self.assertEqual(sim.svstate.srcstep, 0) @@ -66,8 +60,8 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 32 initial_regs[4] = 4 @@ -75,12 +69,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 5) self.assertEqual(sim.svstate.srcstep, 0) @@ -105,30 +99,31 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 32 - initial_regs[4] = 1000 # much greater than MAXVL + initial_regs[4] = 1000 # much greater than MAXVL with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 5) self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) self.assertEqual(sim.svstate.vfirst, 0) print(" gpr4", sim.gpr(4)) - self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified + self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified print(" gpr5", sim.gpr(5)) - self.assertEqual(sim.gpr(5), SelectableInt(5, 64)) # equal to MAXVL + self.assertEqual(sim.gpr(5), SelectableInt(5, 64) + ) # equal to MAXVL CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 0) @@ -147,30 +142,30 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 32 - initial_regs[4] = 1000 # much greater than MAXVL + initial_regs[4] = 1000 # much greater than MAXVL with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 127) self.assertEqual(sim.svstate.maxvl, 127) self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) self.assertEqual(sim.svstate.vfirst, 0) print(" gpr4", sim.gpr(4)) - self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified + self.assertEqual(sim.gpr(4), SelectableInt(1000, 64)) # unmodified print(" gpr5", sim.gpr(5)) - self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL + self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 0) @@ -189,30 +184,30 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 32 - initial_regs[4] = 127 # exactly equal to MAXVL + initial_regs[4] = 127 # exactly equal to MAXVL with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 127) self.assertEqual(sim.svstate.maxvl, 127) self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) self.assertEqual(sim.svstate.vfirst, 0) print(" gpr4", sim.gpr(4)) - self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified + self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified print(" gpr5", sim.gpr(5)) - self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL + self.assertEqual(sim.gpr(5), SelectableInt(127, 64)) # eq. MAXVL CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 0) @@ -231,30 +226,30 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT svstate = SVP64State() - svstate.maxvl = 5 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.maxvl = 5 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 32 - initial_regs[4] = 127 # overlimit, should set CR0.SO=1, and CR0.GT=1 + initial_regs[4] = 127 # overlimit, should set CR0.SO=1, and CR0.GT=1 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 5) self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) self.assertEqual(sim.svstate.vfirst, 0) print(" gpr0", sim.gpr(0)) - self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) # unmodified + self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) # unmodified print(" gpr4", sim.gpr(4)) - self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified + self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 0) @@ -268,28 +263,28 @@ class DecoderTestCase(FHDLTestCase): related to RT_OR_ZERO and to simplev.mdwn pseudocode having _RT not be EXTRA-extended properly """ - lst = SVP64Asm(["sv.setvl 8, 31, 10, 0, 1, 1", # setvl into RT=8 + lst = SVP64Asm(["sv.setvl 8, 31, 10, 0, 1, 1", # setvl into RT=8 ]) lst = list(lst) # SVSTATE (in this case, VL=4) which is going to get erased by setvl svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0] * 64 initial_regs[31] = 200 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=initial_regs, - svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + svstate=svstate) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) self.assertEqual(sim.svstate.srcstep, 0) @@ -300,26 +295,26 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(8), SelectableInt(10, 64)) def test_svstep_1(self): - lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode) - "svstep 0, 1, 0", # svstep - "svstep 0, 1, 0", # svstep + lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode) + "svstep 0, 1, 0", # svstep + "svstep 0, 1, 0", # svstep ]) lst = list(lst) # SVSTATE (in this case, VL=4) which is going to get erased by setvl svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) self.assertEqual(sim.svstate.srcstep, 2) @@ -332,25 +327,25 @@ class DecoderTestCase(FHDLTestCase): """tests svstep when it reaches VL """ lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", # actual setvl (VF mode) - "svstep. 0, 1, 0", # svstep (Rc=1) - "svstep. 0, 1, 0", # svstep (Rc=1) + "svstep. 0, 1, 0", # svstep (Rc=1) + "svstep. 0, 1, 0", # svstep (Rc=1) ]) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate.vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate.vfirst)) self.assertEqual(sim.svstate.vl, 2) self.assertEqual(sim.svstate.maxvl, 2) self.assertEqual(sim.svstate.srcstep, 0) @@ -370,25 +365,25 @@ class DecoderTestCase(FHDLTestCase): """tests svstep when it *doesn't* reach VL """ lst = SVP64Asm(["setvl 0, 0, 3, 1, 1, 1", # actual setvl (VF mode) - "svstep. 0, 1, 0", # svstep (Rc=1) - "svstep. 0, 1, 0", # svstep (Rc=1) + "svstep. 0, 1, 0", # svstep (Rc=1) + "svstep. 0, 1, 0", # svstep (Rc=1) ]) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 3) self.assertEqual(sim.svstate.maxvl, 3) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 @@ -414,18 +409,18 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': 5, - } + } with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_sprs=sprs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) @@ -447,18 +442,18 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': 5, - } + } with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_sprs=sprs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) @@ -481,18 +476,18 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': 0x1000000000, - } + } with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_sprs=sprs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) @@ -514,18 +509,18 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': 0x1000000000, - } + } with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_sprs=sprs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) @@ -540,15 +535,15 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) @@ -563,15 +558,15 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2), want to see if these get changed svstate = SVP64State() - svstate.vl = 10 # VL - svstate.maxvl = 10 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.maxvl, 2) self.assertEqual(sim.svstate.vl, 2) print(" gpr1", sim.gpr(1)) @@ -582,32 +577,32 @@ class DecoderTestCase(FHDLTestCase): also sees if k is actually output into reg 2 (RT=2) """ lst = SVP64Asm([ - # set triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 1", - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 2, 2, 0", # svstep (Rc=1) - ]) + # set triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 1", + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 2, 2, 0", # svstep (Rc=1) + ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 12) self.assertEqual(sim.svstate.maxvl, 12) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 @@ -626,29 +621,29 @@ class DecoderTestCase(FHDLTestCase): """tests svstep inner loop, running 3 times """ lst = SVP64Asm([ - # set triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 1", - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - ]) + # set triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 1", + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 12) self.assertEqual(sim.svstate.maxvl, 12) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 @@ -667,30 +662,30 @@ class DecoderTestCase(FHDLTestCase): """tests svstep inner loop, running 4 times """ lst = SVP64Asm([ - # set triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 1", - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - ]) + # set triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 1", + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 12) self.assertEqual(sim.svstate.maxvl, 12) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 @@ -710,30 +705,30 @@ class DecoderTestCase(FHDLTestCase): "jl" is returned after 4th iteration """ lst = SVP64Asm([ - # set triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 1", - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 0, 2, 0", # svstep (Rc=1) - "svstep. 2, 2, 0", # svstep (Rc=1) - ]) + # set triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 1", + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 0, 2, 0", # svstep (Rc=1) + "svstep. 2, 2, 0", # svstep (Rc=1) + ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 12) self.assertEqual(sim.svstate.maxvl, 12) # svstep called twice, didn't reach VL, so srcstep/dststep both 2 @@ -755,28 +750,28 @@ class DecoderTestCase(FHDLTestCase): fuuun... """ lst = SVP64Asm([ - # set DCT triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 2, 0", - "svremap 0, 0, 0, 2, 0, 1, 1", - "sv.svstep *2, 4, 1", # svstep get vector of ci - "sv.svstep *16, 3, 1", # svstep get vector of step - ]) + # set DCT triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 2, 0", + "svremap 0, 0, 0, 2, 0, 1, 1", + "sv.svstep *2, 4, 1", # svstep get vector of ci + "sv.svstep *16, 3, 1", # svstep get vector of step + ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 12) self.assertEqual(sim.svstate.maxvl, 12) # svstep called four times, reset occurs, srcstep zero @@ -807,9 +802,9 @@ class DecoderTestCase(FHDLTestCase): isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1", 'sv.add *1, *5, *9', "setvl 3, 0, 0, 0, 0, 0", - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -850,18 +845,18 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add *1, *5, *9', - "svstep. 0, 1, 0", # svstep (Rc=1) + "svstep. 0, 1, 0", # svstep (Rc=1) 'sv.add *1, *5, *9', - "svstep. 3, 1, 0", # svstep (Rc=1) - "setvl 4, 0, 0, 0, 0, 0", # getvl + "svstep. 3, 1, 0", # svstep (Rc=1) + "setvl 4, 0, 0, 0, 0, 0", # getvl ]) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -878,12 +873,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 2) self.assertEqual(sim.svstate.maxvl, 2) self.assertEqual(sim.svstate.srcstep, 0) @@ -930,16 +925,16 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add *1, *5, *9', - "svstep. 0, 1, 0", # svstep (Rc=1) - "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!) + "svstep. 0, 1, 0", # svstep (Rc=1) + "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!) ]) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -955,12 +950,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 2) self.assertEqual(sim.svstate.maxvl, 2) self.assertEqual(sim.svstate.srcstep, 0) @@ -983,12 +978,12 @@ class DecoderTestCase(FHDLTestCase): but also uses the same trick when getting the srcstep. """ lst = SVP64Asm(["setvl 0, 0, 5, 1, 1, 1", - 'sv.cmp 0, 1, *4, 14', # r8 contains the temp - 'sv.isel 14,*4,14,1', # copy if cmp was greater - "svstep. 12, 6, 0", # get srcstep - 'sv.isel 10,12,10,1', # copy if cmp was greater - "svstep. 0, 1, 0", # svstep (Rc=1) - "bc 6, 3, -0x24" # branch to cmp + 'sv.cmp 0, 1, *4, 14', # r8 contains the temp + 'sv.isel 14,*4,14,1', # copy if cmp was greater + "svstep. 12, 6, 0", # get srcstep + 'sv.isel 10,12,10,1', # copy if cmp was greater + "svstep. 0, 1, 0", # svstep (Rc=1) + "bc 6, 3, -0x24" # branch to cmp ]) lst = list(lst) @@ -1013,12 +1008,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 5) self.assertEqual(sim.svstate.srcstep, 0) @@ -1045,14 +1040,14 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program) svstate = sim.svstate - print ("SVREMAP after", bin(svstate.value)) - print (" men", bin(svstate.SVme)) - print (" mi0", bin(svstate.mi0)) - print (" mi1", bin(svstate.mi1)) - print (" mi2", bin(svstate.mi2)) - print (" mo0", bin(svstate.mo0)) - print (" mo1", bin(svstate.mo1)) - print (" persist", bin(svstate.RMpst)) + print("SVREMAP after", bin(svstate.value)) + print(" men", bin(svstate.SVme)) + print(" mi0", bin(svstate.mi0)) + print(" mi1", bin(svstate.mi1)) + print(" mi2", bin(svstate.mi2)) + print(" mo0", bin(svstate.mo0)) + print(" mo1", bin(svstate.mo1)) + print(" persist", bin(svstate.RMpst)) self.assertEqual(svstate.SVme, 11) self.assertEqual(svstate.mi0, 0) self.assertEqual(svstate.mi1, 1) @@ -1065,25 +1060,25 @@ class DecoderTestCase(FHDLTestCase): """tests svstep "straight", placing srcstep, dststep into vector """ lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", - "sv.svstep *0, 5, 1", # svstep get vector srcstep - "sv.svstep. *4, 6, 1", # svstep get vector dststep + "sv.svstep *0, 5, 1", # svstep get vector srcstep + "sv.svstep. *4, 6, 1", # svstep get vector dststep ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) # svstep called four times, reset occurs, srcstep zero @@ -1104,16 +1099,16 @@ class DecoderTestCase(FHDLTestCase): """tests svstep "straight", placing srcstep, dststep into vector """ lst = SVP64Asm(["setvl 0, 0, 5, 0, 1, 1", - "sv.svstep/m=r30 *0, 5, 1", # svstep get vector srcstep - "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep + "sv.svstep/m=r30 *0, 5, 1", # svstep get vector srcstep + "sv.svstep./m=r30 *8, 6, 1", # svstep get vector dststep ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) mask = 0b10101 initial_regs = [0] * 32 @@ -1122,12 +1117,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_regs=initial_regs) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) self.assertEqual(sim.svstate.vl, 5) self.assertEqual(sim.svstate.maxvl, 5) # svstep called four times, reset occurs, srcstep zero @@ -1135,7 +1130,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep, 0) sim.gpr.dump() for i in range(5): - if mask & (1< 0b01110 -> 14 isa = SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -108,9 +101,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 10 # VL - svstate.maxvl = 10 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -120,27 +113,27 @@ class SVSTATETestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate=svstate) self._check_regs(sim, expected_regs) - print (sim.spr) + print(sim.spr) SVSHAPE2 = sim.spr['SVSHAPE2'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE2svgpr", hex(SVSHAPE2.svgpr)) - print ("STATE2 xdim", SVSHAPE2.xdimsz) - print ("STATE2 ydim", SVSHAPE2.ydimsz) - print ("STATE2 skip", bin(SVSHAPE2.skip)) - print ("STATE2 inv", SVSHAPE2.invxyz) - print ("STATE2order", SVSHAPE2.order) - self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1 + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE2svgpr", hex(SVSHAPE2.svgpr)) + print("STATE2 xdim", SVSHAPE2.xdimsz) + print("STATE2 ydim", SVSHAPE2.ydimsz) + print("STATE2 skip", bin(SVSHAPE2.skip)) + print("STATE2 inv", SVSHAPE2.invxyz) + print("STATE2order", SVSHAPE2.order) + self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1 # rmm is 0b01110 which means mo0 = 2 self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) @@ -150,13 +143,13 @@ class SVSTATETestCase(FHDLTestCase): # and mo0 should be activated self.assertEqual(sim.svstate.SVme, 0b01000) # now check the SVSHAPEs. 2 was the one targetted - self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1 + self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1 self.assertEqual(SVSHAPE2.xdimsz, 5) # SHAPE2 xdim set to 5 self.assertEqual(SVSHAPE2.ydimsz, 1) # SHAPE2 ydim 1 # all others must be zero - for i in [0,1,3]: + for i in [0, 1, 3]: shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.asint(), 0) # all others zero + self.assertEqual(shape.asint(), 0) # all others zero def test_0_sv_index_add(self): """sets VL=6 (via SVSTATE) then does svindex, and an add. @@ -165,22 +158,22 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -188,37 +181,37 @@ class SVSTATETestCase(FHDLTestCase): RA = initial_regs[0+idxs[i]] RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) @@ -230,65 +223,65 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) for i in range(6): - RA = initial_regs[0+idxs[i%3]] # modulo 3 but still indexed + RA = initial_regs[0+idxs[i % 3]] # modulo 3 but still indexed RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) @@ -301,22 +294,22 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -324,45 +317,45 @@ class SVSTATETestCase(FHDLTestCase): xi = i % 3 yi = i // 3 remap = yi+xi*2 - RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed + RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) @@ -374,13 +367,13 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 1, 3, 0, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): # 8-bit indices starting at reg 16 set_masked_reg(initial_regs, 16, i, ew_bits=8, value=idxs[i]) @@ -388,9 +381,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -398,43 +391,43 @@ class SVSTATETestCase(FHDLTestCase): RA = initial_regs[0+idxs[i]] RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate) @@ -444,4 +437,3 @@ class SVSTATETestCase(FHDLTestCase): if __name__ == "__main__": unittest.main() - diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index 3bcaac46..e5ef3f39 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -1,19 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.consts import SVP64CROffs +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class DecoderTestCase(FHDLTestCase): @@ -40,9 +34,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -58,9 +52,9 @@ class DecoderTestCase(FHDLTestCase): * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 """ isa = SVP64Asm(['sv.add *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -70,13 +64,13 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555 - expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 + expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) @@ -89,9 +83,9 @@ class DecoderTestCase(FHDLTestCase): * r1 is scalar so ENDS EARLY """ isa = SVP64Asm(['sv.add 1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -101,12 +95,12 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) - expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555 + expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) @@ -120,9 +114,9 @@ class DecoderTestCase(FHDLTestCase): * 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 """ isa = SVP64Asm(['sv.add *1, 5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -132,9 +126,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555 @@ -151,9 +145,9 @@ class DecoderTestCase(FHDLTestCase): * none because VL is zero """ isa = SVP64Asm(['sv.add 1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -163,9 +157,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=0) svstate = SVP64State() - svstate.vl = 0 # VL - svstate.maxvl = 0 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 0 # VL + svstate.maxvl = 0 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -182,9 +176,9 @@ class DecoderTestCase(FHDLTestCase): * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 """ isa = SVP64Asm(['sv.add. *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -194,13 +188,13 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x0 - expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 + expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) @@ -209,14 +203,14 @@ class DecoderTestCase(FHDLTestCase): cr1_idx = SVP64CROffs.CR1 CR0 = sim.crl[cr0_idx].get_range().value CR1 = sim.crl[cr1_idx].get_range().value - print ("CR0", CR0) - print ("CR1", CR1) + print("CR0", CR0) + print("CR1", CR1) self._check_regs(sim, expected_regs) self.assertEqual(CR0, SelectableInt(2, 4)) self.assertEqual(CR1, SelectableInt(4, 4)) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate) diff --git a/src/openpower/decoder/isa/test_caller_svp64_alu.py b/src/openpower/decoder/isa/test_caller_svp64_alu.py index 5b10bead..65fd64e1 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_alu.py +++ b/src/openpower/decoder/isa/test_caller_svp64_alu.py @@ -6,8 +6,9 @@ related bugs: """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.alu.svp64_cases import SVP64ALUTestCase +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py index 5e1f1a1d..159f08a2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py @@ -1,19 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.consts import SVP64CROffs +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class DecoderTestCase(FHDLTestCase): @@ -40,9 +34,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -51,24 +45,24 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(9), SelectableInt(0x1235, 64)) def test_sv_branch_cond(self): - for i in [0, 10]: #, 10]: #[0, 10]: + for i in [0, 10]: # , 10]: #[0, 10]: lst = SVP64Asm( [f"addi 1, 0, {i}", # set r1 to i f"addi 2, 0, {i}", # set r2 to i - "cmpi cr0, 1, 1, 10", # compare r1 with 10 and store to cr0 - "cmpi cr1, 1, 2, 10", # compare r2 with 10 and store to cr1 - "sv.bc 12, *2, 0xc", # beq 0xc - - # branch if r1 equals 10 to the nop below - "addi 3, 0, 0x1234", # if r1 == 10 this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "cmpi cr0, 1, 1, 10", # compare r1 with 10 and store to cr0 + "cmpi cr1, 1, 2, 10", # compare r2 with 10 and store to cr1 + "sv.bc 12, *2, 0xc", # beq 0xc - + # branch if r1 equals 10 to the nop below + "addi 3, 0, 0x1234", # if r1 == 10 this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -82,20 +76,20 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm( [f"addi 1, 0, {i+1}", # set r1 to i f"addi 2, 0, {i}", # set r2 to i - "cmpi cr0, 1, 1, 8", # compare r1 with 10 and store to cr0 - "cmpi cr1, 1, 2, 8", # compare r2 with 10 and store to cr1 - "sv.bc/all 12, *1, 0xc", # bgt 0xc - branch if BOTH + "cmpi cr0, 1, 1, 8", # compare r1 with 10 and store to cr0 + "cmpi cr1, 1, 2, 8", # compare r2 with 10 and store to cr1 + "sv.bc/all 12, *1, 0xc", # bgt 0xc - branch if BOTH # r1 AND r2 greater 8 to the nop below - "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "addi 3, 0, 0x1234", # if tests fail this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -109,21 +103,21 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm( [f"addi 1, 0, {i+1}", # set r1 to i f"addi 2, 0, {i}", # set r2 to i - "cmpi cr0, 1, 1, 8", # compare r1 with 10 and store to cr0 - "cmpi cr1, 1, 2, 8", # compare r2 with 10 and store to cr1 - "sv.bc/all/vs 12, *1, 0xc", # bgt 0xc - branch if BOTH + "cmpi cr0, 1, 1, 8", # compare r1 with 10 and store to cr0 + "cmpi cr1, 1, 2, 8", # compare r2 with 10 and store to cr1 + "sv.bc/all/vs 12, *1, 0xc", # bgt 0xc - branch if BOTH # r1 AND r2 greater 8 to the nop below # also truncate VL at the fail-point - "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "addi 3, 0, 0x1234", # if tests fail this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -131,7 +125,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(3), SelectableInt(0, 64)) else: self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) - print ("SVSTATE.vl", bin(svstate.vl)) + print("SVSTATE.vl", bin(svstate.vl)) self.assertEqual(svstate.vl, i-7) def test_sv_branch_cond_vlset_inv(self): @@ -139,26 +133,26 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm( [f"addi 1, 0, {i+1}", # set r1 to i f"addi 2, 0, {i}", # set r2 to i - "cmpi cr0, 1, 1, 8", # compare r1 with 8 and store to cr0 - "cmpi cr1, 1, 2, 8", # compare r2 with 8 and store to cr1 - "sv.bc/vsb 4, *1, 0xc", # bgt 0xc - branch if BOTH + "cmpi cr0, 1, 1, 8", # compare r1 with 8 and store to cr0 + "cmpi cr1, 1, 2, 8", # compare r2 with 8 and store to cr1 + "sv.bc/vsb 4, *1, 0xc", # bgt 0xc - branch if BOTH # r1 AND r2 greater 8 to the nop below # also truncate VL at the fail-point - "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "addi 3, 0, 0x1234", # if tests fail this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with self.subTest("vlset_inv %d" % i): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE.vl", bin(svstate.vl)) + print("SVSTATE.vl", bin(svstate.vl)) if i == 9: self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) else: @@ -170,29 +164,29 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm( [f"addi 1, 0, {i+1}", # set r1 to i f"addi 2, 0, {i}", # set r2 to i - "cmpi cr0, 1, 1, 8", # compare r1 with 8 and store to cr0 - "cmpi cr1, 1, 2, 8", # compare r2 with 8 and store to cr1 - "sv.bc/vsb 0, *1, 0xc", # bgt 0xc - branch if BOTH + "cmpi cr0, 1, 1, 8", # compare r1 with 8 and store to cr0 + "cmpi cr1, 1, 2, 8", # compare r2 with 8 and store to cr1 + "sv.bc/vsb 0, *1, 0xc", # bgt 0xc - branch if BOTH # r1 AND r2 greater 8 to the nop below # also truncate VL at the fail-point - "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "addi 3, 0, 0x1234", # if tests fail this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': i} with self.subTest("vlset_ctr_inv %d" % i): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_sprs=sprs) - print ("SVSTATE.vl", bin(svstate.vl)) - print ("CTR", sim.spr('CTR').value) + print("SVSTATE.vl", bin(svstate.vl)) + print("CTR", sim.spr('CTR').value) if i == 9: self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64)) else: @@ -209,20 +203,20 @@ class DecoderTestCase(FHDLTestCase): however this is not necessarily so useful, but at least the branch occurs with CTR being reduced *at least* by VL. """ - for i in [1,2,3]: + for i in [1, 2, 3]: lst = SVP64Asm( [ - "sv.bc/ctr/all 16, *0, 0xc", # branch, test CTR, reducing by VL - "addi 3, 0, 0x1234", # if tests fail this shouldn't execute - "or 0, 0, 0"] # branch target - ) + "sv.bc/ctr/all 16, *0, 0xc", # branch, test CTR, reducing by VL + "addi 3, 0, 0x1234", # if tests fail this shouldn't execute + "or 0, 0, 0"] # branch target + ) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) sprs = {'CTR': i} with Program(lst, bigendian=False) as program: @@ -245,18 +239,19 @@ class DecoderTestCase(FHDLTestCase): maxvl = 4 lst = SVP64Asm( [ - "setvl 1, 0, %d, 0, 1, 1" % maxvl, # VL (and r1) = MIN(CTR,MAXVL=4) - "add 2, 2, 1", # for fun accumulate r1 (VL) into r2 - "sv.bc/all 16, *0, -0x8", # branch, test CTR, reducing by VL + # VL (and r1) = MIN(CTR,MAXVL=4) + "setvl 1, 0, %d, 0, 1, 1" % maxvl, + "add 2, 2, 1", # for fun accumulate r1 (VL) into r2 + "sv.bc/all 16, *0, -0x8", # branch, test CTR, reducing by VL ] - ) + ) lst = list(lst) # SVSTATE - set vl and maxvl to 2, they get overridden with setvl svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) target = 15 sprs = {'CTR': target} @@ -279,9 +274,9 @@ class DecoderTestCase(FHDLTestCase): * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 """ isa = SVP64Asm(['sv.add. *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -291,13 +286,13 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x0 - expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 + expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) @@ -306,15 +301,15 @@ class DecoderTestCase(FHDLTestCase): cr1_idx = SVP64CROffs.CR1 CR0 = sim.crl[cr0_idx].get_range().value CR1 = sim.crl[cr1_idx].get_range().value - print ("CR0", CR0) - print ("CR1", CR1) + print("CR0", CR0) + print("CR1", CR1) self._check_regs(sim, expected_regs) self.assertEqual(CR0, SelectableInt(2, 4)) self.assertEqual(CR1, SelectableInt(4, 4)) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_sprs=None): + svstate=None, + initial_sprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py index 45973e43..316cea7c 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py @@ -2,8 +2,9 @@ """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.bigint.bigint_cases import SVP64BigIntCases +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py index b402fb41..747d4f03 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_chacha20.py +++ b/src/openpower/decoder/isa/test_caller_svp64_chacha20.py @@ -1,22 +1,15 @@ """SVP64 unit test for svindex svindex SVG,rmm,SVd,ew,yx,mm,sk """ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import (ISACaller, set_masked_reg,) -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State, set_masked_reg +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy # originally from https://github.com/pts/chacha20 @@ -47,19 +40,19 @@ def quarter_round_schedule(x, a, b, c, d): def rotl32(v, c): c = c & 0x1f res = ((v << c) & 0xffffffff) | v >> (32 - c) - print ("op rotl32", hex(res), hex(v), hex(c)) + print("op rotl32", hex(res), hex(v), hex(c)) return res def add(a, b): res = (a + b) & 0xffffffff - print ("op add", hex(res), hex(a), hex(b)) + print("op add", hex(res), hex(a), hex(b)) return res def xor(a, b): res = a ^ b - print ("op xor", hex(res), hex(a), hex(b)) + print("op xor", hex(res), hex(a), hex(b)) return res @@ -68,6 +61,7 @@ def sthth_round(x, a, b, d, rot): x[d] = xor(x[d], x[a]) x[d] = rotl32(x[d], rot) + def quarter_round(x, a, b, c, d): """collate list of reg-offsets for use with svindex/svremap """ @@ -91,11 +85,11 @@ def chacha_idx_schedule(x, fn=quarter_round_schedule): class SVSTATETestCase(FHDLTestCase): def _check_regs(self, sim, expected): - print ("GPR") + print("GPR") sim.gpr.dump() for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64), - "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i])) + "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i])) def test_1_sv_chacha20_main_rounds(self): """chacha20 main rounds @@ -112,34 +106,35 @@ class SVSTATETestCase(FHDLTestCase): *ZERO* branch-prediction misses, obviating a need for loop-unrolling. """ - nrounds = 2 # should be 10 for full algorithm + nrounds = 2 # should be 10 for full algorithm isa = SVP64Asm([ # set up VL=32 vertical-first, and SVSHAPEs 0-2 - 'setvl 17, 0, 32, 1, 0, 1', # vertical-first, set MAXVL (and r17) - 'svindex 11, 0, 1, 3, 0, 1, 0', # SVSHAPE0, a - 'svindex 15, 1, 1, 3, 0, 1, 0', # SVSHAPE1, b - 'svindex 19, 2, 1, 3, 0, 1, 0', # SVSHAPE2, c - 'svindex 21, 3, 4, 3, 0, 1, 0', # SVSHAPE3, shift amount, mod 4 + # vertical-first, set MAXVL (and r17) + 'setvl 17, 0, 32, 1, 0, 1', + 'svindex 11, 0, 1, 3, 0, 1, 0', # SVSHAPE0, a + 'svindex 15, 1, 1, 3, 0, 1, 0', # SVSHAPE1, b + 'svindex 19, 2, 1, 3, 0, 1, 0', # SVSHAPE2, c + 'svindex 21, 3, 4, 3, 0, 1, 0', # SVSHAPE3, shift amount, mod 4 # establish CTR for outer round count 'addi 16, 0, %d' % nrounds, # set number of rounds 'mtspr 9, 16', # set CTR to number of rounds # outer loop begins here (standard CTR loop) 'setvl 17, 17, 32, 1, 1, 0', # vertical-first, set VL from r17 # inner loop begins here. add-xor-rotl32 with remap, step, branch - 'svremap 31, 1, 0, 0, 0, 0, 0', # RA=1, RB=0, RT=0 (0b01011) + 'svremap 31, 1, 0, 0, 0, 0, 0', # RA=1, RB=0, RT=0 (0b01011) 'sv.add/w=32 *0, *0, *0', - 'svremap 31, 2, 0, 2, 2, 0, 0', # RA=2, RB=0, RS=2 (0b00111) + 'svremap 31, 2, 0, 2, 2, 0, 0', # RA=2, RB=0, RS=2 (0b00111) 'sv.xor/w=32 *0, *0, *0', - 'svremap 31, 0, 3, 2, 2, 0, 0', # RA=2, RB=3, RS=2 (0b01110) + 'svremap 31, 0, 3, 2, 2, 0, 0', # RA=2, RB=3, RS=2 (0b01110) 'sv.rldcl/w=32 *0, *0, *18, 0', 'svstep. 16, 1, 0', # step to next in-regs element 'bc 6, 3, -0x28', # svstep. Rc=1 loop-end-condition? # inner-loop done: outer loop standard CTR-decrement to setvl again 'bc 16, 0, -0x30', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) schedule = [] chacha_idx_schedule(schedule, fn=quarter_round_schedule) @@ -148,34 +143,34 @@ class SVSTATETestCase(FHDLTestCase): initial_regs = [0] * 128 # offsets for a b c - for i, (a,b,c,d) in enumerate(schedule): + for i, (a, b, c, d) in enumerate(schedule): set_masked_reg(initial_regs, 22, i, ew_bits=8, value=a) set_masked_reg(initial_regs, 30, i, ew_bits=8, value=b) set_masked_reg(initial_regs, 38, i, ew_bits=8, value=c) # offsets for d (modulo 4 shift amount) - shifts = [16, 12, 8, 7] # chacha20 shifts - idxs2 = [0, 1, 2, 3] # cycle order (for fun) + shifts = [16, 12, 8, 7] # chacha20 shifts + idxs2 = [0, 1, 2, 3] # cycle order (for fun) for i in range(4): set_masked_reg(initial_regs, 42, i, ew_bits=8, value=idxs2[i]) set_masked_reg(initial_regs, 18, i, ew_bits=32, value=shifts[i]) x = [0] * 16 for i in range(16): - x[i] = i<<1 + x[i] = i << 1 for i in range(16): set_masked_reg(initial_regs, 0, i, ew_bits=32, value=x[i]) # SVSTATE vl=32 svstate = SVP64State() - svstate.vl = 32 # VL - svstate.maxvl = 32 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 32 # VL + svstate.maxvl = 32 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running, compute expected results expected_regs = deepcopy(initial_regs) expected_regs[16] = 0 # reaches zero - expected_regs[17] = 32 # gets set to MAXVL + expected_regs[17] = 32 # gets set to MAXVL expected = deepcopy(x) for i in range(nrounds): chacha_idx_schedule(expected, fn=quarter_round) @@ -188,30 +183,30 @@ class SVSTATETestCase(FHDLTestCase): # print out expected regs for i in range(8): RS = sim.gpr(i).value - print ("expected", i, hex(RS), hex(expected_regs[i])) + print("expected", i, hex(RS), hex(expected_regs[i])) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] SVSHAPE1 = sim.spr['SVSHAPE1'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - print (sim.gpr.dump()) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + print(sim.gpr.dump()) self._check_regs(sim, expected_regs) self.assertEqual(sim.svstate.RMpst, 0) self.assertEqual(sim.svstate.SVme, 0b11111) @@ -224,7 +219,7 @@ class SVSTATETestCase(FHDLTestCase): self.assertEqual(SVSHAPE1.svgpr, 30) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate) @@ -234,4 +229,3 @@ class SVSTATETestCase(FHDLTestCase): if __name__ == "__main__": unittest.main() - diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py index c9312ef4..35e74226 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dct.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py @@ -1,22 +1,17 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle +import math +import unittest + from nmutil.formaltest import FHDLTestCase -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.simulator.program import Program +from openpower.decoder.helpers import SINGLE, fp64toselectable from openpower.decoder.isa.caller import SVP64State -from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.isa.remap_dct_yield import ( + halfrev2, inverse_transform2, iterate_dct_inner_butterfly_indices, + iterate_dct_outer_butterfly_indices, reverse_bits, transform2) from openpower.decoder.isa.test_caller import run_tst -from openpower.sv.trans.svp64 import SVP64Asm -from copy import deepcopy -from openpower.decoder.helpers import fp64toselectable, SINGLE from openpower.decoder.isafunctions.double2single import ISACallerFnHelper -from openpower.decoder.isa.remap_dct_yield import (halfrev2, reverse_bits, - iterate_dct_inner_butterfly_indices, - iterate_dct_outer_butterfly_indices, - transform2, inverse_transform2) -from openpower.decoder.isa.fastdctlee import inverse_transform_iter -import unittest -import math +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.sv.trans.svp64 import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. @@ -27,8 +22,8 @@ def transform_inner_radix2_dct(vec, ctable): # Initialization n = len(vec) - print () - print ("transform2", n) + print() + print("transform2", n) levels = n.bit_length() - 1 # reference (read/write) the in-place data in *reverse-bit-order* @@ -57,7 +52,7 @@ def transform_inner_radix2_dct(vec, ctable): SVSHAPE0.submode2 = 0b01 SVSHAPE0.skip = 0b00 SVSHAPE0.offset = 0 # experiment with different offset, here - SVSHAPE0.invxyz = [1,0,0] # inversion if desired + SVSHAPE0.invxyz = [1, 0, 0] # inversion if desired # j+halfstep schedule SVSHAPE1 = SVSHAPE() SVSHAPE1.lims = [xdim, 2, zdim] @@ -65,7 +60,7 @@ def transform_inner_radix2_dct(vec, ctable): SVSHAPE1.submode2 = 0b01 SVSHAPE1.skip = 0b01 SVSHAPE1.offset = 0 # experiment with different offset, here - SVSHAPE1.invxyz = [1,0,0] # inversion if desired + SVSHAPE1.invxyz = [1, 0, 0] # inversion if desired # enumerate over the iterator function, getting new indices i0 = iterate_dct_inner_butterfly_indices(SVSHAPE0) @@ -75,12 +70,12 @@ def transform_inner_radix2_dct(vec, ctable): coeff = ctable[k] vec[jl] = t1 + t2 vec[jh] = (t1 - t2) * (1.0/coeff) - print ("coeff", "ci", k, - "jl", jl, "jh", jh, - "i/n", (k+0.5), 1.0/coeff, - "t1, t2", t1, t2, "res", vec[jl], vec[jh], - "end", bin(jle), bin(jhe)) - if jle == 0b111: # all loops end + print("coeff", "ci", k, + "jl", jl, "jh", jh, + "i/n", (k+0.5), 1.0/coeff, + "t1, t2", t1, t2, "res", vec[jl], vec[jh], + "end", bin(jle), bin(jhe)) + if jle == 0b111: # all loops end break return vec @@ -90,8 +85,8 @@ def transform_outer_radix2_dct(vec): # Initialization n = len(vec) - print () - print ("transform2", n) + print() + print("transform2", n) levels = n.bit_length() - 1 # outer butterfly @@ -108,7 +103,7 @@ def transform_outer_radix2_dct(vec): SVSHAPE0.mode = 0b01 SVSHAPE0.skip = 0b00 SVSHAPE0.offset = 0 # experiment with different offset, here - SVSHAPE0.invxyz = [0,0,0] # inversion if desired + SVSHAPE0.invxyz = [0, 0, 0] # inversion if desired # j+halfstep schedule SVSHAPE1 = SVSHAPE() SVSHAPE1.lims = [xdim, 3, zdim] @@ -116,16 +111,16 @@ def transform_outer_radix2_dct(vec): SVSHAPE1.submode2 = 0b100 SVSHAPE1.skip = 0b01 SVSHAPE1.offset = 0 # experiment with different offset, here - SVSHAPE1.invxyz = [0,0,0] # inversion if desired + SVSHAPE1.invxyz = [0, 0, 0] # inversion if desired # enumerate over the iterator function, getting new indices i0 = iterate_dct_outer_butterfly_indices(SVSHAPE0) i1 = iterate_dct_outer_butterfly_indices(SVSHAPE1) for k, ((jl, jle), (jh, jhe)) in enumerate(zip(i0, i1)): - print ("itersum jr", jl, jh, - "end", bin(jle), bin(jhe)) + print("itersum jr", jl, jh, + "end", bin(jle), bin(jhe)) vec[jl] += vec[jh] - if jle == 0b111: # all loops end + if jle == 0b111: # all loops end break print("transform2 result", vec) @@ -137,8 +132,8 @@ def transform_inner_radix2_idct(vec, ctable): # Initialization n = len(vec) - print () - print ("transform2", n) + print() + print("transform2", n) levels = n.bit_length() - 1 # pretend we LDed data in half-swapped order @@ -161,7 +156,7 @@ def transform_inner_radix2_idct(vec, ctable): SVSHAPE0.submode2 = 0b11 SVSHAPE0.skip = 0b00 SVSHAPE0.offset = 0 # experiment with different offset, here - SVSHAPE0.invxyz = [0,0,0] # inversion if desired + SVSHAPE0.invxyz = [0, 0, 0] # inversion if desired # j+halfstep schedule SVSHAPE1 = SVSHAPE() SVSHAPE1.lims = [xdim, 0b000001, 1] @@ -169,7 +164,7 @@ def transform_inner_radix2_idct(vec, ctable): SVSHAPE1.submode2 = 0b11 SVSHAPE1.skip = 0b01 SVSHAPE1.offset = 0 # experiment with different offset, here - SVSHAPE1.invxyz = [0,0,0] # inversion if desired + SVSHAPE1.invxyz = [0, 0, 0] # inversion if desired # enumerate over the iterator function, getting new indices i0 = iterate_dct_inner_butterfly_indices(SVSHAPE0) @@ -179,12 +174,12 @@ def transform_inner_radix2_idct(vec, ctable): coeff = ctable[k] vec[jl] = t1 + t2/coeff vec[jh] = t1 - t2/coeff - print ("coeff", "ci", k, - "jl", jl, "jh", jh, - "i/n", (k+0.5), 1.0/coeff, - "t1, t2", t1, t2, "res", vec[jl], vec[jh], - "end", bin(jle), bin(jhe)) - if jle == 0b111: # all loops end + print("coeff", "ci", k, + "jl", jl, "jh", jh, + "i/n", (k+0.5), 1.0/coeff, + "t1, t2", t1, t2, "res", vec[jl], vec[jh], + "end", bin(jle), bin(jhe)) + if jle == 0b111: # all loops end break return vec @@ -194,8 +189,8 @@ def transform_outer_radix2_idct(vec): # Initialization n = len(vec) - print () - print ("transform2-inv", n) + print() + print("transform2-inv", n) levels = n.bit_length() - 1 # outer butterfly @@ -221,7 +216,7 @@ def transform_outer_radix2_idct(vec): SVSHAPE0.mode = 0b11 SVSHAPE0.skip = 0b00 SVSHAPE0.offset = 0 # experiment with different offset, here - SVSHAPE0.invxyz = [1,0,1] # inversion if desired + SVSHAPE0.invxyz = [1, 0, 1] # inversion if desired # j+halfstep schedule SVSHAPE1 = SVSHAPE() SVSHAPE1.lims = [xdim, 2, zdim] @@ -229,16 +224,16 @@ def transform_outer_radix2_idct(vec): SVSHAPE1.submode2 = 0b011 SVSHAPE1.skip = 0b01 SVSHAPE1.offset = 0 # experiment with different offset, here - SVSHAPE1.invxyz = [1,0,1] # inversion if desired + SVSHAPE1.invxyz = [1, 0, 1] # inversion if desired # enumerate over the iterator function, getting new indices i0 = iterate_dct_outer_butterfly_indices(SVSHAPE0) i1 = iterate_dct_outer_butterfly_indices(SVSHAPE1) for k, ((jl, jle), (jh, jhe)) in enumerate(zip(i0, i1)): - print ("itersum jr", jl, jh, - "end", bin(jle), bin(jhe)) + print("itersum jr", jl, jh, + "end", bin(jle), bin(jhe)) vec[jh] += vec[jl] - if jle == 0b111: # all loops end + if jle == 0b111: # all loops end break print("transform2-inv result", vec) @@ -271,8 +266,8 @@ class DCTTestCase(FHDLTestCase): # cheat here with these values, they're selected so that # rounding errors do not occur. sigh. fprs = [0] * 32 - av = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 - bv = [-2.0, 2.0, -0.8, 1.4] # second half of array 4..7 + av = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 + bv = [-2.0, 2.0, -0.8, 1.4] # second half of array 4..7 cv = [-1.0, 0.5, 2.5, -0.25] # coefficients res = [] # work out the results with the twin add-sub @@ -285,19 +280,19 @@ class DCTTestCase(FHDLTestCase): # and FPSUB32 directly to be honest. t = a + b diff = (a - b) - diff = fph.DOUBLE2SINGLE(fp64toselectable(diff)) # FP32 round + diff = fph.DOUBLE2SINGLE(fp64toselectable(diff)) # FP32 round diff = float(diff) u = diff * c - tc = fph.DOUBLE2SINGLE(fp64toselectable(t)) # cvt to Power single - uc = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double + tc = fph.DOUBLE2SINGLE(fp64toselectable(t)) # cvt to Power single + uc = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double res.append((uc, tc)) - print ("DCT", i, "in", a, b, "c", c, "res", t, u) + print("DCT", i, "in", a, b, "c", c, "res", t, u) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -308,7 +303,7 @@ class DCTTestCase(FHDLTestCase): b = float(sim.fpr(i+4)) t = float(t) u = float(u) - print ("DCT", i, "in", a, b, "res", t, u) + print("DCT", i, "in", a, b, "res", t, u) for i, (t, u) in enumerate(res): self.assertEqual(sim.fpr(i+0), t) self.assertEqual(sim.fpr(i+4), u) @@ -334,47 +329,47 @@ class DCTTestCase(FHDLTestCase): is straight Vectorised (0123...) because DCT coefficients cannot be shared between butterfly layers (due to +0.5) """ - lst = SVP64Asm( ["svshape 4, 1, %d, 2, 0" % stride, - "svremap 27, 1, 0, 2, 0, 1, 0", - "sv.fdmadds *0, *0, *0, *16" + lst = SVP64Asm(["svshape 4, 1, %d, 2, 0" % stride, + "svremap 27, 1, 0, 2, 0, 1, 0", + "sv.fdmadds *0, *0, *0, *16" ]) lst = list(lst) # array and coefficients to test n = 4 av = [7.0, -9.8, 3.0, -32.3] - coe = [-0.25, 0.5, 3.1, 6.2] # 4 coefficients + coe = [-0.25, 0.5, 3.1, 6.2] # 4 coefficients levels = n.bit_length() - 1 ri = list(range(n)) ri = [ri[reverse_bits(i, levels)] for i in range(n)] - avi = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 + avi = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 av = halfrev2(avi, False) av = [av[ri[i]] for i in range(n)] # store in regfile fprs = [0] * 64 for i, c in enumerate(coe): - fprs[i+16] = fp64toselectable(1.0 / c) # invert + fprs[i+16] = fp64toselectable(1.0 / c) # invert for i, a in enumerate(av): fprs[i*stride+0] = fp64toselectable(a) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_inner_radix2_dct(avi, coe) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -384,7 +379,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-6) def test_sv_remap_fpmadds_idct_inner_4_stride_1(self): @@ -408,42 +403,42 @@ class DCTTestCase(FHDLTestCase): is straight Vectorised (0123...) because DCT coefficients cannot be shared between butterfly layers (due to +0.5) """ - lst = SVP64Asm( ["svshape 4, 1, %d, 10, 0" % stride, - "svremap 27, 0, 1, 2, 1, 0, 0", - "sv.ffmadds *0, *0, *0, *16" + lst = SVP64Asm(["svshape 4, 1, %d, 10, 0" % stride, + "svremap 27, 0, 1, 2, 1, 0, 0", + "sv.ffmadds *0, *0, *0, *16" ]) lst = list(lst) # array and coefficients to test n = 4 levels = n.bit_length() - 1 - coe = [-0.25, 0.5, 3.1, 6.2] # 4 coefficients - avi = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 + coe = [-0.25, 0.5, 3.1, 6.2] # 4 coefficients + avi = [7.0, -0.8, 2.0, -2.3] # first half of array 0..3 av = halfrev2(avi, False) # store in regfile fprs = [0] * 64 for i, c in enumerate(coe): - fprs[i+16] = fp64toselectable(1.0 / c) # invert + fprs[i+16] = fp64toselectable(1.0 / c) # invert for i, a in enumerate(av): fprs[i*stride+0] = fp64toselectable(a) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_inner_radix2_idct(avi, coe) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -453,7 +448,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-6) def test_sv_remap_fpmadds_idct_outer_8(self, stride=2): @@ -466,9 +461,9 @@ class DCTTestCase(FHDLTestCase): SVP64 "REMAP" in Butterfly Mode. """ - lst = SVP64Asm( ["svshape 8, 1, %d, 11, 0" % stride, # outer butterfly - "svremap 27, 0, 1, 2, 1, 0, 0", - "sv.fadds *0, *0, *0" + lst = SVP64Asm(["svshape 8, 1, %d, 11, 0" % stride, # outer butterfly + "svremap 27, 0, 1, 2, 1, 0, 0", + "sv.fadds *0, *0, *0" ]) lst = list(lst) @@ -489,20 +484,20 @@ class DCTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = transform_outer_radix2_idct(avi) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -512,7 +507,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-6) def test_sv_remap_fpmadds_dct_outer_8(self, stride=2): @@ -525,9 +520,9 @@ class DCTTestCase(FHDLTestCase): SVP64 "REMAP" in Butterfly Mode. """ - lst = SVP64Asm( ["svshape 8, 1, %d, 3, 0" % stride, - "svremap 27, 1, 0, 2, 0, 1, 0", - "sv.fadds *0, *0, *0" + lst = SVP64Asm(["svshape 8, 1, %d, 3, 0" % stride, + "svremap 27, 1, 0, 2, 0, 1, 0", + "sv.fadds *0, *0, *0" ]) lst = list(lst) @@ -541,20 +536,20 @@ class DCTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = transform_outer_radix2_dct(av) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -564,7 +559,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-6) def test_sv_remap_fpmadds_idct_8(self, stride=2): @@ -577,11 +572,11 @@ class DCTTestCase(FHDLTestCase): runs a full in-place 8-long O(N log2 N) inverse-DCT, both inner and outer butterfly "REMAP" schedules. """ - lst = SVP64Asm( ["svremap 27, 0, 1, 2, 1, 0, 1", - "svshape 8, 1, %d, 11, 0" % stride, - "sv.fadds *0, *0, *0", - "svshape 8, 1, %d, 10, 0" % stride, - "sv.ffmadds *0, *0, *0, *16" + lst = SVP64Asm(["svremap 27, 0, 1, 2, 1, 0, 1", + "svshape 8, 1, %d, 11, 0" % stride, + "sv.fadds *0, *0, *0", + "svshape 8, 1, %d, 10, 0" % stride, + "sv.ffmadds *0, *0, *0, *16" ]) lst = list(lst) @@ -599,7 +594,7 @@ class DCTTestCase(FHDLTestCase): av[0] /= 2.0 #avi[0] /= 2.0 - print ("input data pre idct", av) + print("input data pre idct", av) ctable = [] size = 2 @@ -615,17 +610,17 @@ class DCTTestCase(FHDLTestCase): for i, a in enumerate(av): fprs[i*stride+0] = fp64toselectable(a) for i, c in enumerate(ctable): - fprs[i+16] = fp64toselectable(1.0 / c) # invert + fprs[i+16] = fp64toselectable(1.0 / c) # invert with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # inverse DCT expected = [-15.793373940443367, 27.46969091937703, @@ -636,8 +631,8 @@ class DCTTestCase(FHDLTestCase): #res = transform_outer_radix2_idct(avi) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -647,7 +642,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i*stride, err) + print("err", i*stride, err) self.assertTrue(err < 1e-5) def test_sv_remap_fpmadds_dct_8(self, stride=2): @@ -660,11 +655,11 @@ class DCTTestCase(FHDLTestCase): runs a full in-place 8-long O(N log2 N) DCT, both inner and outer butterfly "REMAP" schedules. """ - lst = SVP64Asm( ["svremap 27, 1, 0, 2, 0, 1, 1", - "svshape 8, 1, %d, 2, 0" % stride, - "sv.fdmadds *0, *0, *0, *16", - "svshape 8, 1, %d, 3, 0" % stride, - "sv.fadds *0, *0, *0" + lst = SVP64Asm(["svremap 27, 1, 0, 2, 0, 1, 1", + "svshape 8, 1, %d, 2, 0" % stride, + "sv.fdmadds *0, *0, *0, *16", + "svshape 8, 1, %d, 3, 0" % stride, + "sv.fadds *0, *0, *0" ]) lst = list(lst) @@ -690,24 +685,24 @@ class DCTTestCase(FHDLTestCase): for i, a in enumerate(av): fprs[i*stride+0] = fp64toselectable(a) for i, c in enumerate(ctable): - fprs[i+16] = fp64toselectable(1.0 / c) # invert + fprs[i+16] = fp64toselectable(1.0 / c) # invert with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = transform2(avi) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -717,7 +712,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-5) def test_sv_remap_dct_cos_precompute_8(self): @@ -732,8 +727,8 @@ class DCTTestCase(FHDLTestCase): """ lst = SVP64Asm(["svshape 8, 1, 1, 2, 0", "svremap 0, 0, 0, 2, 0, 1, 1", - "sv.svstep *4, 4, 1", # svstep get vector of ci - "sv.svstep *16, 3, 1", # svstep get vector of step + "sv.svstep *4, 4, 1", # svstep get vector of ci + "sv.svstep *16, 3, 1", # svstep get vector of step "addi 1, 0, 0x0000", "setvl 0, 0, 12, 0, 1, 1", "sv.std *4, 0(1)", @@ -743,19 +738,19 @@ class DCTTestCase(FHDLTestCase): "sv.std *16, 0(1)", "sv.lfd *12, 0(1)", "sv.fcfids *24, *12", - "sv.fadds *0, *24, 43", # plus 0.5 - "sv.fmuls *0, *0, 41", # times PI - "sv.fdivs *0, *0, *48", # div size + "sv.fadds *0, *24, 43", # plus 0.5 + "sv.fmuls *0, *0, 41", # times PI + "sv.fdivs *0, *0, *48", # div size "sv.fcoss *80, *0", - "sv.fdivs *80, 43, *80", # div 0.5 / x - ]) + "sv.fdivs *80, 43, *80", # div 0.5 / x + ]) lst = list(lst) gprs = [0] * 32 fprs = [0] * 128 # constants fprs[43] = fp64toselectable(0.5) # 0.5 - fprs[41] = fp64toselectable(math.pi) # pi + fprs[41] = fp64toselectable(math.pi) # pi fprs[44] = fp64toselectable(2.0) # 2.0 n = 8 @@ -771,27 +766,27 @@ class DCTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, gprs, initial_fprs=fprs) - print ("MEM") + print("MEM") sim.mem.dump() - print ("ci FP") + print("ci FP") for i in range(len(ctable)): actual = float(sim.fpr(i+24)) - print ("i", i, actual) - print ("size FP") + print("i", i, actual) + print("size FP") for i in range(len(ctable)): actual = float(sim.fpr(i+48)) - print ("i", i, actual) - print ("temps") + print("i", i, actual) + print("temps") for i in range(len(ctable)): actual = float(sim.fpr(i)) - print ("i", i, actual) + print("i", i, actual) for i in range(len(ctable)): expected = 1.0/ctable[i] actual = float(sim.fpr(i+80)) err = abs((actual - expected) / expected) - print ("i", i, actual, "1/expect", 1/expected, - "expected", expected, - "err", err) + print("i", i, actual, "1/expect", 1/expected, + "expected", expected, + "err", err) self.assertTrue(err < 1e-6) def test_sv_remap_dct_cos_precompute_inner_8(self): @@ -806,8 +801,8 @@ class DCTTestCase(FHDLTestCase): """ lst = SVP64Asm(["svshape 8, 1, 1, 5, 0", "svremap 0, 0, 0, 2, 0, 1, 1", - "sv.svstep *4, 3, 1", # svstep get vector of ci - "sv.svstep *16, 2, 1", # svstep get vector of step + "sv.svstep *4, 3, 1", # svstep get vector of ci + "sv.svstep *16, 2, 1", # svstep get vector of step "addi 1, 0, 0x0000", "setvl 0, 0, 7, 0, 1, 1", "sv.std *4, 0(1)", @@ -817,19 +812,19 @@ class DCTTestCase(FHDLTestCase): "sv.std *16, 0(1)", "sv.lfd *12, 0(1)", "sv.fcfids *24, *12", - "sv.fadds *0, *24, 43", # plus 0.5 - "sv.fmuls *0, *0, 41", # times PI - "sv.fdivs *0, *0, *48", # div size + "sv.fadds *0, *24, 43", # plus 0.5 + "sv.fmuls *0, *0, 41", # times PI + "sv.fdivs *0, *0, *48", # div size "sv.fcoss *80, *0", - "sv.fdivs *80, 43, *80", # div 0.5 / x - ]) + "sv.fdivs *80, 43, *80", # div 0.5 / x + ]) lst = list(lst) gprs = [0] * 32 fprs = [0] * 128 # constants fprs[43] = fp64toselectable(0.5) # 0.5 - fprs[41] = fp64toselectable(math.pi) # pi + fprs[41] = fp64toselectable(math.pi) # pi fprs[44] = fp64toselectable(2.0) # 2.0 n = 8 @@ -841,33 +836,33 @@ class DCTTestCase(FHDLTestCase): for ci in range(halfsize): coeff = math.cos((ci + 0.5) * math.pi / size) * 2.0 ctable.append(coeff) - print ("coeff", "ci", ci, "size", size, - "i/n", (ci+0.5), 1.0/coeff) + print("coeff", "ci", ci, "size", size, + "i/n", (ci+0.5), 1.0/coeff) size //= 2 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, gprs, initial_fprs=fprs) - print ("MEM") + print("MEM") sim.mem.dump() - print ("ci FP") + print("ci FP") for i in range(len(ctable)): actual = float(sim.fpr(i+24)) - print ("i", i, actual) - print ("size FP") + print("i", i, actual) + print("size FP") for i in range(len(ctable)): actual = float(sim.fpr(i+48)) - print ("i", i, actual) - print ("temps") + print("i", i, actual) + print("temps") for i in range(len(ctable)): actual = float(sim.fpr(i)) - print ("i", i, actual) + print("i", i, actual) for i in range(len(ctable)): expected = 1.0/ctable[i] actual = float(sim.fpr(i+80)) err = abs((actual - expected) / expected) - print ("i", i, actual, "1/expect", 1/expected, - "expected", expected, - "err", err) + print("i", i, actual, "1/expect", 1/expected, + "expected", expected, + "err", err) self.assertTrue(err < 1e-6) def test_sv_remap_fpmadds_dct_8_mode_4(self, stride=2): @@ -881,11 +876,11 @@ class DCTTestCase(FHDLTestCase): inner and outer butterfly "REMAP" schedules. uses shorter tables: FRC also needs to be on a Schedule """ - lst = SVP64Asm( ["svremap 31, 1, 0, 2, 0, 1, 1", - "svshape 8, 1, %d, 4, 0" % stride, - "sv.fdmadds *0, *0, *0, *16", - "svshape 8, 1, %d, 3, 0" % stride, - "sv.fadds *0, *0, *0" + lst = SVP64Asm(["svremap 31, 1, 0, 2, 0, 1, 1", + "svshape 8, 1, %d, 4, 0" % stride, + "sv.fdmadds *0, *0, *0, *16", + "svshape 8, 1, %d, 3, 0" % stride, + "sv.fadds *0, *0, *0" ]) lst = list(lst) @@ -910,24 +905,24 @@ class DCTTestCase(FHDLTestCase): for i, a in enumerate(av): fprs[i*stride+0] = fp64toselectable(a) for i, c in enumerate(ctable): - fprs[i+16] = fp64toselectable(1.0 / c) # invert + fprs[i+16] = fp64toselectable(1.0 / c) # invert with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = transform2(avi) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -937,7 +932,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-5) def test_sv_remap_fpmadds_ldbrev_dct_8_mode_4(self, stride=1): @@ -959,15 +954,15 @@ class DCTTestCase(FHDLTestCase): uses shorter pre-loaded COS tables: FRC also needs to be on a Schedule """ - lst = SVP64Asm( ["addi 1, 0, 0x000", - "svshape 8, 1, %d, 6, 0" % stride, - "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfs/els *0, 4(1)", - "svremap 31, 1, 0, 2, 0, 1, 1", - "svshape 8, 1, %d, 4, 0" % stride, - "sv.fdmadds *0, *0, *0, *32", - "svshape 8, 1, %d, 3, 0" % stride, - "sv.fadds *0, *0, *0" + lst = SVP64Asm(["addi 1, 0, 0x000", + "svshape 8, 1, %d, 6, 0" % stride, + "svremap 1, 0, 0, 0, 0, 0, 0", + "sv.lfs/els *0, 4(1)", + "svremap 31, 1, 0, 2, 0, 1, 1", + "svshape 8, 1, %d, 4, 0" % stride, + "sv.fdmadds *0, *0, *0, *32", + "svshape 8, 1, %d, 3, 0" % stride, + "sv.fadds *0, *0, *0" ]) lst = list(lst) @@ -984,7 +979,8 @@ class DCTTestCase(FHDLTestCase): if shift == 0: val = a # accumulate for next iteration else: - mem[(i//2)*8] = val | (a << 32) # even and odd 4-byte in same 8 + # even and odd 4-byte in same 8 + mem[(i//2)*8] = val | (a << 32) # calculate the (shortened) COS tables, 4 2 1 not 4 2+2 1+1+1+1 n = len(avi) @@ -999,25 +995,25 @@ class DCTTestCase(FHDLTestCase): # store in regfile fprs = [0] * 64 for i, c in enumerate(ctable): - fprs[i+32] = fp64toselectable(1.0 / c) # invert + fprs[i+32] = fp64toselectable(1.0 / c) # invert with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs, - initial_mem=mem) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + initial_mem=mem) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = transform2(avi) for i, expected in enumerate(res): - print ("i", i*stride, float(sim.fpr(i*stride)), - "expected", expected) + print("i", i*stride, float(sim.fpr(i*stride)), + "expected", expected) for i, expected in enumerate(res): # convert to Power single @@ -1028,7 +1024,7 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-5) def test_sv_remap_fpmadds_ldbrev_idct_8_mode_4(self): @@ -1050,15 +1046,15 @@ class DCTTestCase(FHDLTestCase): uses shorter pre-loaded COS tables: FRC also needs to be on a Schedule in the sv.ffmadds instruction """ - lst = SVP64Asm( ["addi 1, 0, 0x000", - "svshape 8, 1, 1, 14, 0", - "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfs/els *0, 4(1)", - "svremap 31, 0, 1, 2, 1, 0, 1", - "svshape 8, 1, 1, 11, 0", - "sv.fadds *0, *0, *0", - "svshape 8, 1, 1, 12, 0", - "sv.ffmadds *0, *0, *0, *8" + lst = SVP64Asm(["addi 1, 0, 0x000", + "svshape 8, 1, 1, 14, 0", + "svremap 1, 0, 0, 0, 0, 0, 0", + "sv.lfs/els *0, 4(1)", + "svremap 31, 0, 1, 2, 1, 0, 1", + "svshape 8, 1, 1, 11, 0", + "sv.fadds *0, *0, *0", + "svshape 8, 1, 1, 12, 0", + "sv.ffmadds *0, *0, *0, *8" ]) lst = list(lst) @@ -1070,14 +1066,15 @@ class DCTTestCase(FHDLTestCase): mem = {} val = 0 for i, a in enumerate(avi): - if i == 0: # first element, divide by 2 + if i == 0: # first element, divide by 2 a /= 2.0 a = SINGLE(fp64toselectable(a)).value shift = (i % 2) == 1 if shift == 0: val = a # accumulate for next iteration else: - mem[(i//2)*8] = val | (a << 32) # even and odd 4-byte in same 8 + # even and odd 4-byte in same 8 + mem[(i//2)*8] = val | (a << 32) # calculate the (shortened) COS tables, 4 2 1 not 4 2+2 1+1+1+1 n = len(avi) @@ -1092,24 +1089,24 @@ class DCTTestCase(FHDLTestCase): # store in regfile fprs = [0] * 32 for i, c in enumerate(ctable): - fprs[i+8] = fp64toselectable(1.0 / c) # invert + fprs[i+8] = fp64toselectable(1.0 / c) # invert with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs, - initial_mem=mem) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + initial_mem=mem) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # outer iterative sum res = inverse_transform2(avi) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single @@ -1120,22 +1117,22 @@ class DCTTestCase(FHDLTestCase): # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different err = abs((actual - expected) / expected) - print ("err", i, err) + print("err", i, err) self.assertTrue(err < 1e-5) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py index af5fb470..40e31b1c 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py @@ -1,22 +1,12 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy -from openpower.decoder.helpers import fp64toselectable -from functools import reduce -import operator class DecoderTestCase(FHDLTestCase): @@ -26,15 +16,15 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) def test_sv_addi_ffirst_le(self): - lst = SVP64Asm([ "sv.subf./ff=le *0,8,*0" + lst = SVP64Asm(["sv.subf./ff=le *0,8,*0" ]) lst = list(lst) # SVSTATE svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 gprs[8] = 3 @@ -47,11 +37,11 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) + svstate=svstate) for i in range(4): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected expected = deepcopy(vec) expected_vl = 0 @@ -71,15 +61,15 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep, 0) def test_sv_addi_ffirst(self): - lst = SVP64Asm([ "sv.subf./ff=eq *0,8,*0" + lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0" ]) lst = list(lst) # SVSTATE svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 gprs[8] = 3 @@ -92,11 +82,11 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) + svstate=svstate) for i in range(4): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected expected = deepcopy(vec) for i in range(4): @@ -113,15 +103,15 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep, 0) def test_sv_addi_ffirst_rc1(self): - lst = SVP64Asm([ "sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1) + lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0" # RC1 auto-sets EQ (and Rc=1) ]) lst = list(lst) # SVSTATE svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 gprs[8] = 3 @@ -134,11 +124,11 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) + svstate=svstate) for i in range(4): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected expected = deepcopy(vec) for i in range(4): @@ -155,15 +145,15 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep, 0) def test_sv_addi_ffirst_vli(self): - lst = SVP64Asm([ "sv.subf/ff=RC1/vli *0,8,*0" + lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0" ]) lst = list(lst) # SVSTATE svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 gprs[8] = 3 @@ -176,11 +166,11 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) + svstate=svstate) for i in range(4): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected expected = deepcopy(vec) for i in range(4): @@ -196,18 +186,18 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.svstate.dststep, 0) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_elwidth.py b/src/openpower/decoder/isa/test_caller_svp64_elwidth.py index 4f6a8727..6ad3cdba 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_elwidth.py +++ b/src/openpower/decoder/isa/test_caller_svp64_elwidth.py @@ -6,8 +6,9 @@ related bugs: """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.alu.svp64_cases import SVP64ALUElwidthTestCase +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py index d5985755..14df7a31 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fft.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py @@ -1,16 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.simulator.program import Program + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.helpers import SINGLE, fp64toselectable from openpower.decoder.isa.caller import SVP64State -from openpower.decoder.selectable_int import SelectableInt from openpower.decoder.isa.test_caller import run_tst -from openpower.sv.trans.svp64 import SVP64Asm -from copy import deepcopy -from openpower.decoder.helpers import fp64toselectable, SINGLE from openpower.decoder.isafunctions.double2single import ISACallerFnHelper +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.sv.trans.svp64 import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. @@ -56,10 +53,10 @@ def transform_radix2(vec, exptable, reverse=False): temp2 = vec[jl] vec[jh] = temp2 - temp1 vec[jl] = temp2 + temp1 - print ("xform jl jh k", jl, jh, k, - "vj vjh ek", temp2, vjh, exptable[k], - "t1, t2", temp1, temp2, - "v[jh] v[jl]", vec[jh], vec[jl]) + print("xform jl jh k", jl, jh, k, + "vj vjh ek", temp2, vjh, exptable[k], + "t1, t2", temp1, temp2, + "v[jh] v[jl]", vec[jh], vec[jl]) k += tablestep size *= 2 @@ -101,30 +98,30 @@ def transform_radix2_complex(vec_r, vec_i, cos_r, sin_i, reverse=False): # triple-nested for-loops jl, jh = j, j+halfsize - print ("xform jl jh k", jl, jh, k, - "vr h l", vec_r[jh], vec_r[jl], - "vi h l", vec_i[jh], vec_i[jl]) - print (" cr k", cos_r[k], "si k", sin_i[k]) - mul1_r = vec_r[jh] * cos_r[k] + print("xform jl jh k", jl, jh, k, + "vr h l", vec_r[jh], vec_r[jl], + "vi h l", vec_i[jh], vec_i[jl]) + print(" cr k", cos_r[k], "si k", sin_i[k]) + mul1_r = vec_r[jh] * cos_r[k] mul2_r = vec_i[jh] * sin_i[k] - tpre = mul1_r + mul2_r - print (" vec_r[jh] * cos_r[k]", mul1_r) - print (" vec_i[jh] * sin_i[k]", mul2_r) - print (" tpre", tpre) + tpre = mul1_r + mul2_r + print(" vec_r[jh] * cos_r[k]", mul1_r) + print(" vec_i[jh] * sin_i[k]", mul2_r) + print(" tpre", tpre) mul1_i = vec_r[jh] * sin_i[k] mul2_i = vec_i[jh] * cos_r[k] tpim = -mul1_i + mul2_i - print (" vec_r[jh] * sin_i[k]", mul1_i) - print (" vec_i[jh] * cos_r[k]", mul2_i) - print (" tpim", tpim) + print(" vec_r[jh] * sin_i[k]", mul1_i) + print(" vec_i[jh] * cos_r[k]", mul2_i) + print(" tpim", tpim) vec_r[jh] = vec_r[jl] - tpre vec_i[jh] = vec_i[jl] - tpim vec_r[jl] += tpre vec_i[jl] += tpim - print (" xform jl jh k", jl, jh, k, - "\n vr h l", vec_r[jh], vec_r[jl], - "\n vi h l", vec_i[jh], vec_i[jl]) + print(" xform jl jh k", jl, jh, k, + "\n vr h l", vec_r[jh], vec_r[jl], + "\n vi h l", vec_i[jh], vec_i[jl]) k += tablestep size *= 2 @@ -147,15 +144,15 @@ class FFTTestCase(FHDLTestCase): are not actually tested because there's no checking yet on FP Rc=1 """ - lst = SVP64Asm( ["svshape 2, 1, 1, 1, 0", - "svremap 31, 1, 0, 2, 0, 1, 0", + lst = SVP64Asm(["svshape 2, 1, 1, 1, 0", + "svremap 31, 1, 0, 2, 0, 1, 0", "sv.ffmadds *0, *0, *0, *8" ]) lst = list(lst) # array and coefficients to test - av = [7.0, -9.8 ] # array 0..1 - coe = [3.1] # coefficients + av = [7.0, -9.8] # array 0..1 + coe = [3.1] # coefficients # store in regfile fprs = [0] * 32 @@ -166,19 +163,19 @@ class FFTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_radix2(av, coe) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -207,16 +204,16 @@ class FFTTestCase(FHDLTestCase): SVP64 "REMAP" in Butterfly Mode is applied to a twin +/- FMAC (3 inputs, 2 outputs) """ - lst = SVP64Asm( ["svshape 8, 1, 1, 1, 0", - "svremap 31, 1, 0, 2, 0, 1, 0", + lst = SVP64Asm(["svshape 8, 1, 1, 1, 0", + "svremap 31, 1, 0, 2, 0, 1, 0", "sv.ffmadds *0, *0, *0, *8" ]) lst = list(lst) # array and coefficients to test av = [7.0, -9.8, 3.0, -32.3, - -2.0, 5.0, -9.8, 31.3] # array 0..7 - coe = [-0.25, 0.5, 3.1, 6.2] # coefficients + -2.0, 5.0, -9.8, 31.3] # array 0..7 + coe = [-0.25, 0.5, 3.1, 6.2] # coefficients # store in regfile fprs = [0] * 32 @@ -227,19 +224,19 @@ class FFTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_radix2(av, coe) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -267,19 +264,19 @@ class FFTTestCase(FHDLTestCase): SVP64 "REMAP" in Butterfly Mode is applied to a twin +/- FMAC (3 inputs, 2 outputs) """ - lst = SVP64Asm( [ - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 0", - "sv.ffmadds *0, *0, *0, *8", - "svstep. 27, 1, 0", - "bc 6, 3, -16" - ]) + lst = SVP64Asm([ + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 0", + "sv.ffmadds *0, *0, *0, *8", + "svstep. 27, 1, 0", + "bc 6, 3, -16" + ]) lst = list(lst) # array and coefficients to test av = [7.0, -9.8, 3.0, -32.3, - -2.0, 5.0, -9.8, 31.3] # array 0..7 - coe = [-0.25, 0.5, 3.1, 6.2] # coefficients + -2.0, 5.0, -9.8, 31.3] # array 0..7 + coe = [-0.25, 0.5, 3.1, 6.2] # coefficients # store in regfile fprs = [0] * 32 @@ -303,26 +300,26 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl = VL # VL - svstate.maxvl = VL # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_radix2(av, coe) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -374,23 +371,23 @@ class FFTTestCase(FHDLTestCase): only one persistent svremap is needed. the exact same trick *could* be applied here but for illustrative purposes it is not. """ - lst = SVP64Asm( [ - "svshape 8, 1, 1, 1, 1", - # RA: jh (S1) RB: n/a RC: k (S2) RT: scalar EA: n/a - "svremap 5, 1, 0, 2, 0, 0, 0", - "sv.fmuls 24, *0, *8", - # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1) - "svremap 26, 0, 0, 0, 0, 1, 0", - "sv.ffadds *0, 24, *0", - "svstep. 27, 1, 0", - "bc 6, 3, -28" - ]) + lst = SVP64Asm([ + "svshape 8, 1, 1, 1, 1", + # RA: jh (S1) RB: n/a RC: k (S2) RT: scalar EA: n/a + "svremap 5, 1, 0, 2, 0, 0, 0", + "sv.fmuls 24, *0, *8", + # RA: scal RB: jl (S0) RC: n/a RT: jl (S0) EA: jh (S1) + "svremap 26, 0, 0, 0, 0, 1, 0", + "sv.ffadds *0, 24, *0", + "svstep. 27, 1, 0", + "bc 6, 3, -28" + ]) lst = list(lst) # array and coefficients to test av = [7.0, -9.8, 3.0, -32.3, - -2.0, 5.0, -9.8, 31.3] # array 0..7 - coe = [-0.25, 0.5, 3.1, 6.2] # coefficients + -2.0, 5.0, -9.8, 31.3] # array 0..7 + coe = [-0.25, 0.5, 3.1, 6.2] # coefficients # store in regfile fprs = [0] * 32 @@ -414,26 +411,26 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl = VL # VL - svstate.maxvl = VL # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub res = transform_radix2(av, coe) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -469,8 +466,8 @@ class FFTTestCase(FHDLTestCase): lst = list(lst) fprs = [0] * 32 - av = [7.0, -9.8, 2.0, -32.3] # first half of array 0..3 - bv = [-2.0, 2.0, -9.8, 32.3] # second half of array 4..7 + av = [7.0, -9.8, 2.0, -32.3] # first half of array 0..3 + bv = [-2.0, 2.0, -9.8, 32.3] # second half of array 4..7 coe = [-1.0, 4.0, 3.1, 6.2] # coefficients res = [] # work out the results with the twin mul/add-sub @@ -481,16 +478,17 @@ class FFTTestCase(FHDLTestCase): mul = a * c t = b + mul u = b - mul - t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single - u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double + # convert to Power single + t = fph.DOUBLE2SINGLE(fp64toselectable(t)) + u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double res.append((t, u)) - print ("FFT", i, "in", a, b, "coeff", c, "mul", mul, "res", t, u) + print("FFT", i, "in", a, b, "coeff", c, "mul", mul, "res", t, u) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -517,8 +515,8 @@ class FFTTestCase(FHDLTestCase): lst = list(lst) fprs = [0] * 32 - av = [7.0, -9.8, 2.0, -32.3] # first half of array 0..3 - bv = [-2.0, 2.0, -9.8, 32.3] # second half of array 4..7 + av = [7.0, -9.8, 2.0, -32.3] # first half of array 0..3 + bv = [-2.0, 2.0, -9.8, 32.3] # second half of array 4..7 res = [] # work out the results with the twin add-sub for i, (a, b) in enumerate(zip(av, bv)): @@ -526,16 +524,17 @@ class FFTTestCase(FHDLTestCase): fprs[i+6] = fp64toselectable(b) t = b + a u = b - a - t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single - u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double + # convert to Power single + t = fph.DOUBLE2SINGLE(fp64toselectable(t)) + u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double res.append((t, u)) - print ("FFT", i, "in", a, b, "res", t, u) + print("FFT", i, "in", a, b, "res", t, u) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -546,7 +545,7 @@ class FFTTestCase(FHDLTestCase): b = float(sim.fpr(i+6)) t = float(t) u = float(u) - print ("FFT", i, "in", a, b, "res", t, u) + print("FFT", i, "in", a, b, "res", t, u) for i, (t, u) in enumerate(res): self.assertEqual(sim.fpr(i+2), t) self.assertEqual(sim.fpr(i+6), u) @@ -598,36 +597,36 @@ class FFTTestCase(FHDLTestCase): "svremap 31, 1, 0, 2, 0, 1, 1", and save one instruction. """ - lst = SVP64Asm( [ - # set triple butterfly mode with persistent "REMAP" - "svshape 8, 1, 1, 1, 1", - "svremap 31, 1, 0, 2, 0, 1, 1", - # tpre - "sv.fmuls 24, *0, *16", # mul1_r = r*cos_r - "sv.fmadds 24, *8, *20, 24", # mul2_r = i*sin_i - # tpre = mul1_r + mul2_r - # tpim - "sv.fmuls 26, *0, *20", # mul1_i = r*sin_i - "sv.fmsubs 26, *8, *16, 26", # mul2_i = i*cos_r - # tpim = mul2_i - mul1_i - # vec_r jh/jl - "sv.ffadds *0, 24, *0", # vh/vl +/- tpre - # vec_i jh/jl - "sv.ffadds *8, 26, *8", # vh/vl +- tpim - - # svstep loop - "svstep. 27, 1, 0", - "bc 6, 3, -56" - ]) + lst = SVP64Asm([ + # set triple butterfly mode with persistent "REMAP" + "svshape 8, 1, 1, 1, 1", + "svremap 31, 1, 0, 2, 0, 1, 1", + # tpre + "sv.fmuls 24, *0, *16", # mul1_r = r*cos_r + "sv.fmadds 24, *8, *20, 24", # mul2_r = i*sin_i + # tpre = mul1_r + mul2_r + # tpim + "sv.fmuls 26, *0, *20", # mul1_i = r*sin_i + "sv.fmsubs 26, *8, *16, 26", # mul2_i = i*cos_r + # tpim = mul2_i - mul1_i + # vec_r jh/jl + "sv.ffadds *0, 24, *0", # vh/vl +/- tpre + # vec_i jh/jl + "sv.ffadds *8, 26, *8", # vh/vl +- tpim + + # svstep loop + "svstep. 27, 1, 0", + "bc 6, 3, -56" + ]) lst = list(lst) # array and coefficients to test ar = [7.0, -9.8, 3.0, -32.3, - -2.0, 5.0, -9.8, 31.3] # array 0..7 real + -2.0, 5.0, -9.8, 31.3] # array 0..7 real ai = [1.0, -1.8, 3.0, 19.3, - 4.0, -2.0, -0.8, 1.3] # array 0..7 imaginary - coer = [-0.25, 0.5, 3.1, 6.2] # coefficients real - coei = [0.21, -0.1, 1.1, -4.0] # coefficients imaginary + 4.0, -2.0, -0.8, 1.3] # array 0..7 imaginary + coer = [-0.25, 0.5, 3.1, 6.2] # coefficients real + coei = [0.21, -0.1, 1.1, -4.0] # coefficients imaginary # store in regfile fprs = [0] * 64 @@ -655,47 +654,47 @@ class FFTTestCase(FHDLTestCase): # SVSTATE (calculated VL) svstate = SVP64State() - svstate.vl = VL # VL - svstate.maxvl = VL # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = VL # VL + svstate.maxvl = VL # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # work out the results with the twin mul/add-sub, explicit # complex numbers res_r, res_i = transform_radix2_complex(ar, ai, coer, coei) for i, (expected_r, expected_i) in enumerate(zip(res_r, res_i)): - print ("i", i, float(sim.fpr(i)), float(sim.fpr(i+8)), - "expected_r", expected_r, - "expected_i", expected_i) + print("i", i, float(sim.fpr(i)), float(sim.fpr(i+8)), + "expected_r", expected_r, + "expected_i", expected_i) for i, (expected_r, expected_i) in enumerate(zip(res_r, res_i)): # convert to Power single - expected_r = fph.DOUBLE2SINGLE(fp64toselectable(expected_r )) + expected_r = fph.DOUBLE2SINGLE(fp64toselectable(expected_r)) expected_r = float(expected_r) actual_r = float(sim.fpr(i)) # approximate error calculation, good enough test # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different - err = abs(actual_r - expected_r ) / expected_r + err = abs(actual_r - expected_r) / expected_r self.assertTrue(err < 1e-6) # convert to Power single - expected_i = fph.DOUBLE2SINGLE(fp64toselectable(expected_i )) + expected_i = fph.DOUBLE2SINGLE(fp64toselectable(expected_i)) expected_i = float(expected_i) actual_i = float(sim.fpr(i+8)) # approximate error calculation, good enough test # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB # and the rounding is different - err = abs(actual_i - expected_i ) / expected_i + err = abs(actual_i - expected_i) / expected_i self.assertTrue(err < 1e-6) def test_sv_ffadds_fft_scalar(self): @@ -718,16 +717,17 @@ class FFTTestCase(FHDLTestCase): for i in range(4): t = scalar_b + scalar_a u = scalar_b - scalar_a - t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single - u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double + # convert to Power single + t = fph.DOUBLE2SINGLE(fp64toselectable(t)) + u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # from double res.append((t, u)) - print ("FFT", i, "res", t, u) + print("FFT", i, "res", t, u) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -738,7 +738,7 @@ class FFTTestCase(FHDLTestCase): b = float(sim.fpr(i+6)) t = float(t) u = float(u) - print ("FFT", i, "in", a, b, "res", t, u) + print("FFT", i, "in", a, b, "res", t, u) for i, (t, u) in enumerate(res): self.assertEqual(sim.fpr(i+2), t) self.assertEqual(sim.fpr(i+6), u) @@ -753,19 +753,19 @@ class FFTTestCase(FHDLTestCase): runs a full in-place O(N log2 N) butterfly schedule for Discrete Fourier Transform, using bit-reversed LD/ST """ - lst = SVP64Asm( ["svshape 8, 1, 1, 15, 0", - "svremap 1, 0, 0, 0, 0, 0, 0", - "sv.lfs/els *0, 4(0)", - "svshape 8, 1, 1, 1, 0", - "svremap 31, 1, 0, 2, 0, 1, 0", - "sv.ffmadds *0, *0, *0, *8" + lst = SVP64Asm(["svshape 8, 1, 1, 15, 0", + "svremap 1, 0, 0, 0, 0, 0, 0", + "sv.lfs/els *0, 4(0)", + "svshape 8, 1, 1, 1, 0", + "svremap 31, 1, 0, 2, 0, 1, 0", + "sv.ffmadds *0, *0, *0, *8" ]) lst = list(lst) # array and coefficients to test av = [7.0, -9.8, 3.0, -32.3, - -2.0, 5.0, -9.8, 31.3] # array 0..7 - coe = [-0.25, 0.5, 3.1, 6.2] # coefficients + -2.0, 5.0, -9.8, 31.3] # array 0..7 + coe = [-0.25, 0.5, 3.1, 6.2] # coefficients # store in regfile fprs = [0] * 32 @@ -784,24 +784,24 @@ class FFTTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_mem=mem, - initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) - - print ("mem dump") - print (sim.mem.dump()) + initial_fprs=fprs) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) + + print("mem dump") + print(sim.mem.dump()) # work out the results with the twin mul/add-sub, # note bit-reverse mode requested res = transform_radix2(av, coe, reverse=True) for i, expected in enumerate(res): - print ("i", i, float(sim.fpr(i)), "expected", expected) + print("i", i, float(sim.fpr(i)), "expected", expected) for i, expected in enumerate(res): # convert to Power single expected = fph.DOUBLE2SINGLE(fp64toselectable(expected)) @@ -814,18 +814,18 @@ class FFTTestCase(FHDLTestCase): self.assertTrue(err < 1e-6) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_fp.py b/src/openpower/decoder/isa/test_caller_svp64_fp.py index 610fb59f..703e95ab 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fp.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fp.py @@ -1,19 +1,11 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class DecoderTestCase(FHDLTestCase): @@ -32,26 +24,26 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # memory addresses 0x0000 and 0x0008 - initial_mem = {0x0000: (0x42013333, 8), # 32.3 - 0x0008: (0xC0200000, 8), # -2.5 - } + initial_mem = {0x0000: (0x42013333, 8), # 32.3 + 0x0008: (0xC0200000, 8), # -2.5 + } # and RB will move on from 0 for first iteration to 1 in 2nd # therefore we must point GPR(0) at initial mem 0x0000 # and GPR(1) at initial mem 0x0008 initial_regs = [0] * 32 - initial_regs[0] = 0x0000 # points at memory address 0x0000 (element 0) - initial_regs[1] = 0x0008 # points at memory address 0x0008 (element 1) + initial_regs[0] = 0x0000 # points at memory address 0x0000 (element 0) + initial_regs[1] = 0x0008 # points at memory address 0x0008 (element 1) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, - svstate=svstate, - initial_mem=initial_mem) + svstate=svstate, + initial_mem=initial_mem) print(sim.fpr(2)) print(sim.fpr(3)) self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64)) @@ -94,36 +86,36 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm(["sv.lfsx *0, 0, *4", "sv.stfsu *0, 16(*4)", "sv.lfs *2, 0(*4)", - ]) + ]) lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # memory addresses 0x0000 and 0x0008 - initial_mem = {0x0000: (0x42013333, 8), # 32.3 - 0x0008: (0xC0200000, 8), # -2.5 + initial_mem = {0x0000: (0x42013333, 8), # 32.3 + 0x0008: (0xC0200000, 8), # -2.5 0x0020: (0x1828384822324252, 8), - } + } # and RB will move on from 0 for first iteration to 1 in 2nd # therefore we must point GPR(4) at initial mem 0x0000 # and GPR(5) at initial mem 0x0008 initial_regs = [0] * 32 - initial_regs[4] = 0x0000 # points at memory address 0x0000 (element 0) - initial_regs[5] = 0x0008 # points at memory address 0x0008 (element 1) + initial_regs[4] = 0x0000 # points at memory address 0x0000 (element 0) + initial_regs[5] = 0x0008 # points at memory address 0x0008 (element 1) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, - svstate=svstate, - initial_mem=initial_mem) + svstate=svstate, + initial_mem=initial_mem) print("FPR 1", sim.fpr(0)) print("FPR 2", sim.fpr(1)) - print("GPR 1", sim.gpr(4)) # should be 0x10 due to update - print("GPR 2", sim.gpr(5)) # should be 0x18 due to update + print("GPR 1", sim.gpr(4)) # should be 0x10 due to update + print("GPR 2", sim.gpr(5)) # should be 0x18 due to update self.assertEqual(sim.gpr(4), SelectableInt(0x10, 64)) self.assertEqual(sim.gpr(5), SelectableInt(0x18, 64)) self.assertEqual(sim.fpr(0), SelectableInt(0x4040266660000000, 64)) @@ -140,16 +132,16 @@ class DecoderTestCase(FHDLTestCase): lst = list(lst) fprs = [0] * 32 - fprs[2] = 0xC040266660000000 # -32.3 - fprs[3] = 0xC040266660000000 # -32.3 - fprs[4] = 0x4040266660000000 # +32.3 - fprs[5] = 0xC040266660000000 # -32.3 + fprs[2] = 0xC040266660000000 # -32.3 + fprs[3] = 0xC040266660000000 # -32.3 + fprs[4] = 0x4040266660000000 # +32.3 + fprs[5] = 0xC040266660000000 # -32.3 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -172,16 +164,16 @@ class DecoderTestCase(FHDLTestCase): fprs[2] = 0x401C000000000000 # 7.0 fprs[3] = 0xC02399999999999A # -9.8 fprs[4] = 0x4000000000000000 # 2.0 - fprs[5] = 0xC040266660000000 # -32.3 + fprs[5] = 0xC040266660000000 # -32.3 fprs[6] = 0x4000000000000000 # 2.0 fprs[7] = 0x4000000000000000 # 2.0 fprs[8] = 0xc000000000000000 # -2.0 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -190,18 +182,18 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(7), SelectableInt(0x4073a8a3c0000000, 64)) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_fptrans.py b/src/openpower/decoder/isa/test_caller_svp64_fptrans.py index c8529897..9b23de87 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_fptrans.py +++ b/src/openpower/decoder/isa/test_caller_svp64_fptrans.py @@ -2,8 +2,9 @@ """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.fptrans.fptrans_cases import SVP64FPTransCases +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py index d54a59c9..454bf09d 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py +++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py @@ -1,23 +1,11 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy -from openpower.decoder.helpers import fp64toselectable -from openpower.decoder.isa.remap_preduce_yield import preduce_y -from functools import reduce -import operator def signcopy(x, y): @@ -40,35 +28,35 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 vec = [1, 2, 3] - crs_expected = [8, 2, 0] # LT EQ GT + crs_expected = [8, 2, 0] # LT EQ GT res = [] # store GPRs for i, x in enumerate(vec): gprs[i+16] = x - gprs[0] = 2 # middle value of vec + gprs[0] = 2 # middle value of vec with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) - print ("spr svstate ", sim.svstate) - print (" vl", sim.svstate.vl) + svstate=svstate) + print("spr svstate ", sim.svstate) + print(" vl", sim.svstate.vl) for i in range(len(vec)): val = sim.gpr(16+i).value res.append(val) crf = sim.crl[i].get_range().value - print ("i", i, val, crf) + print("i", i, val, crf) for i in range(len(vec)): crf = sim.crl[i].get_range().value assert crf == crs_expected[i], "cr %d %s expect %s" % \ - (i, crf, crs_expected[i]) + (i, crf, crs_expected[i]) assert sim.svstate.vl == 2 def test_sv_cmp_ff(self): @@ -78,35 +66,35 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 vec = [1, 2, 3] - crs_expected = [8, 2, 0] # LT EQ GT + crs_expected = [8, 2, 0] # LT EQ GT res = [] # store GPRs for i, x in enumerate(vec): gprs[i+16] = x - gprs[0] = 2 # middle value of vec + gprs[0] = 2 # middle value of vec with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) - print ("spr svstate ", sim.svstate) - print (" vl", sim.svstate.vl) + svstate=svstate) + print("spr svstate ", sim.svstate) + print(" vl", sim.svstate.vl) for i in range(len(vec)): val = sim.gpr(16+i).value res.append(val) crf = sim.crl[i].get_range().value - print ("i", i, val, crf) + print("i", i, val, crf) for i in range(len(vec)): crf = sim.crl[i].get_range().value assert crf == crs_expected[i], "cr %d %s expect %s" % \ - (i, crf, crs_expected[i]) + (i, crf, crs_expected[i]) assert sim.svstate.vl == 1 def test_sv_cmp_ff_lt(self): @@ -116,35 +104,35 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 vec = [1, 2, 3] - crs_expected = [8, 2, 4] # LT EQ GT + crs_expected = [8, 2, 4] # LT EQ GT res = [] # store GPRs for i, x in enumerate(vec): gprs[i+16] = x - gprs[0] = 2 # middle value of vec + gprs[0] = 2 # middle value of vec with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) - print ("spr svstate ", sim.svstate) - print (" vl", sim.svstate.vl) + svstate=svstate) + print("spr svstate ", sim.svstate) + print(" vl", sim.svstate.vl) for i in range(len(vec)): val = sim.gpr(16+i).value res.append(val) crf = sim.crl[i].get_range().value - print ("i", i, val, crf) + print("i", i, val, crf) for i in range(len(vec)): crf = sim.crl[i].get_range().value assert crf == crs_expected[i], "cr %d %s expect %s" % \ - (i, crf, crs_expected[i]) + (i, crf, crs_expected[i]) assert sim.svstate.vl == 2 def test_sv_cmp(self): @@ -154,30 +142,30 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) gprs = [0] * 64 vec = [1, 2, 3] - crs_expected = [8, 2, 4] # LT EQ GT + crs_expected = [8, 2, 4] # LT EQ GT res = [] # store GPRs for i, x in enumerate(vec): gprs[i+16] = x - gprs[0] = 2 # middle value of vec + gprs[0] = 2 # middle value of vec with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs, - svstate=svstate) - print ("spr svstate ", sim.spr['SVSTATE']) + svstate=svstate) + print("spr svstate ", sim.spr['SVSTATE']) for i in range(len(vec)): val = sim.gpr(16+i).value res.append(val) crf = sim.crl[i].get_range().value - print ("i", i, val, crf) + print("i", i, val, crf) assert crf == crs_expected[i] def test_sv_insert_sort(self): @@ -240,19 +228,19 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs) - print ("spr svstate ", sim.spr['SVSTATE']) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svstate ", sim.spr['SVSTATE']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(len(vec)): val = sim.gpr(16+i).value res.append(val) crf = sim.crl[i].get_range().value - print ("i", i, val, crf) + print("i", i, val, crf) return # confirm that the results are as expected expected = list(reversed(sorted(vec))) @@ -260,18 +248,18 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(v, expected[i]) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py index b4c2f9b4..647e7935 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py +++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py @@ -1,22 +1,15 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.helpers import fp64toselectable +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.remap_dct_yield import halfrev2, reverse_bits +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from openpower.decoder.helpers import fp64toselectable -from openpower.decoder.isa.remap_dct_yield import (halfrev2, reverse_bits, - ) -from copy import deepcopy + def write_byte(mem, addr, val): addr, offs = (addr // 8)*8, (addr % 8)*8 @@ -45,38 +38,43 @@ class DecoderTestCase(FHDLTestCase): maxvl = 4 lst = SVP64Asm( [ - "mtspr 9, 3", # move r3 to CTR - "addi 0,0,0", # initialise r0 to zero - # chr-copy loop starts here: - # for (i = 0; i < n && src[i] != '\0'; i++) - # dest[i] = src[i]; - "setvl 1,0,%d,0,1,1" % maxvl, # VL (and r1) = MIN(CTR,MAXVL=4) - "sv.lbzu/pi *16, 1(10)", # load VL bytes (update r10 addr) - "sv.cmpi/ff=eq/vli *0,1,*16,0", # compare against zero, truncate VL - "sv.stbu/pi *16, 1(12)", # store VL bytes (update r12 addr) - "sv.bc/all 0, *2, -0x1c", # test CTR, stop if cmpi failed - # zeroing loop starts here: - # for ( ; i < n; i++) - # dest[i] = '\0'; - "setvl 1,0,%d,0,1,1" % maxvl, # VL (and r1) = MIN(CTR,MAXVL=4) - "sv.stbu/pi 0, 1(12)", # store VL zeros (update r12 addr) - "sv.bc 16, *0, -0xc", # decrement CTR by VL, stop at zero + "mtspr 9, 3", # move r3 to CTR + "addi 0,0,0", # initialise r0 to zero + # chr-copy loop starts here: + # for (i = 0; i < n && src[i] != '\0'; i++) + # dest[i] = src[i]; + # VL (and r1) = MIN(CTR,MAXVL=4) + "setvl 1,0,%d,0,1,1" % maxvl, + # load VL bytes (update r10 addr) + "sv.lbzu/pi *16, 1(10)", + "sv.cmpi/ff=eq/vli *0,1,*16,0", # compare against zero, truncate VL + # store VL bytes (update r12 addr) + "sv.stbu/pi *16, 1(12)", + "sv.bc/all 0, *2, -0x1c", # test CTR, stop if cmpi failed + # zeroing loop starts here: + # for ( ; i < n; i++) + # dest[i] = '\0'; + # VL (and r1) = MIN(CTR,MAXVL=4) + "setvl 1,0,%d,0,1,1" % maxvl, + # store VL zeros (update r12 addr) + "sv.stbu/pi 0, 1(12)", + "sv.bc 16, *0, -0xc", # decrement CTR by VL, stop at zero ] - ) + ) lst = list(lst) tst_string = "hello\x00bye\x00" initial_regs = [0] * 32 - initial_regs[3] = len(tst_string) # including the zero - initial_regs[10] = 16 # load address - initial_regs[12] = 40 # store address + initial_regs[3] = len(tst_string) # including the zero + initial_regs[10] = 16 # load address + initial_regs[12] = 40 # store address # some memory with identifying garbage in it initial_mem = {16: 0xf0f1_f2f3_f4f5_f6f7, 24: 0x4041_4243_4445_4647, 40: 0x8081_8283_8485_8687, 48: 0x9091_9293_9495_9697, - } + } for i, c in enumerate(tst_string): write_byte(initial_mem, 16+i, ord(c)) @@ -98,7 +96,7 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_mem=initial_mem, - initial_regs=initial_regs) + initial_regs=initial_regs) mem = sim.mem.dump(printout=True, asciidump=True) #print (mem) # contents of memory expected at: @@ -107,7 +105,7 @@ class DecoderTestCase(FHDLTestCase): # therefore, at address 0x10 ==> 0x1234 # therefore, at address 0x28 ==> 0x1235 for (k, val) in expected_mem.items(): - print ("mem, val", k, hex(val)) + print("mem, val", k, hex(val)) self.assertEqual(mem, list(expected_mem.items())) print(sim.gpr(1)) # reg 10 (the LD EA) is expected to be nearest @@ -115,7 +113,8 @@ class DecoderTestCase(FHDLTestCase): rounded = ((strlen+maxvl-1) // maxvl) * maxvl self.assertEqual(sim.gpr(10), SelectableInt(16+rounded, 64)) # whereas reg 10 (the ST EA) is expected to be 40+strlen - self.assertEqual(sim.gpr(12), SelectableInt(40+len(tst_string), 64)) + self.assertEqual(sim.gpr(12), SelectableInt( + 40+len(tst_string), 64)) def test_sv_load_store_postinc(self): """>>> lst = ["addi 20, 0, 0x0010", @@ -153,14 +152,14 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) mem = sim.mem.dump(printout=False) - print (mem) + print(mem) # contents of memory expected at: # element 0: r1=0x10, D=24, => EA = 0x10+24*0 = 16 (0x10) # element 1: r1=0x10, D=24, => EA = 0x10+24*1 = 40 (0x28) @@ -198,19 +197,19 @@ class DecoderTestCase(FHDLTestCase): "addi 4, 0, 0x1234", "addi 5, 0, 0x1235", "sv.stw/els *4, 24(2)", # scalar r1 + 16 + 24*offs - "sv.lwz/els *8, 24(2)"]) # scalar r1 + 16 + 24*offs + "sv.lwz/els *8, 24(2)"]) # scalar r1 + 16 + 24*offs lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) mem = sim.mem.dump(printout=False) - print (mem) + print(mem) # contents of memory expected at: # element 0: r1=0x10, D=24, => EA = 0x10+24*0 = 16 (0x10) # element 1: r1=0x10, D=24, => EA = 0x10+24*1 = 40 (0x28) @@ -243,20 +242,20 @@ class DecoderTestCase(FHDLTestCase): "addi 8, 0, 0x1234", "addi 9, 0, 0x1235", "sv.stw *8, 8(1)", # scalar r1 + 8 + wordlen*offs - "sv.lwz *12, 8(1)"]) # scalar r1 + 8 + wordlen*offs + "sv.lwz *12, 8(1)"]) # scalar r1 + 8 + wordlen*offs lst = list(lst) # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) mem = sim.mem.dump(printout=False) - print ("Mem") - print (mem) + print("Mem") + print(mem) # contents of memory expected at: # element 0: r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*0 = 0x24 # element 1: r1=0x10, D=8, wordlen=4 => EA = 0x10+8+4*8 = 0x28 @@ -290,19 +289,19 @@ class DecoderTestCase(FHDLTestCase): "addi 6, 0, 0x303", "addi 7, 0, 0x404", "sv.stw *4, 0(1)", # scalar r1 + 0 + wordlen*offs - "sv.lwzsh *12, 4(1), 2"]) # bit-reversed + "sv.lwzsh *12, 4(1), 2"]) # bit-reversed lst = list(lst) # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) mem = sim.mem.dump(printout=False) - print (mem) + print(mem) self.assertEqual(mem, [(16, 0x020200000101), (24, 0x040400000303)]) @@ -349,29 +348,29 @@ class DecoderTestCase(FHDLTestCase): "addi 5, 0, 0x202", "addi 6, 0, 0x303", "addi 7, 0, 0x404", - "sv.std *4, 0(1)", # scalar r1 + 0 + wordlen*offs - "sv.lfdsh *12, 8(1), 2"]) # shifted + "sv.std *4, 0(1)", # scalar r1 + 0 + wordlen*offs + "sv.lfdsh *12, 8(1), 2"]) # shifted lst = list(lst) # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) fprs = [0] * 32 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_fprs=fprs) + initial_fprs=fprs) mem = sim.mem.dump(printout=False) - print (mem) + print(mem) self.assertEqual(mem, [(16, 0x101), (24, 0x202), (32, 0x303), (40, 0x404), - ]) + ]) print(sim.gpr(1)) # from STs self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64)) @@ -409,14 +408,14 @@ class DecoderTestCase(FHDLTestCase): lst = SVP64Asm(["addi 1, 0, 0x0010", "addi 2, 0, 0x0000", "sv.stfs *4, 0(1)", # scalar r1 + 0 + wordlen*offs - "sv.lfssh *12, 4(1), 2"]) # shifted (by zero, but hey) + "sv.lfssh *12, 4(1), 2"]) # shifted (by zero, but hey) lst = list(lst) # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 4 # VL - svstate.maxvl = 4 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 4 # VL + svstate.maxvl = 4 # MAXVL + print("SVSTATE", bin(svstate.asint())) fprs = [0] * 32 scalar_a = 1.3 @@ -428,22 +427,22 @@ class DecoderTestCase(FHDLTestCase): # expected results, remember that bit-reversed load has been done expected_fprs = deepcopy(fprs) - expected_fprs[12] = fprs[4] # 0b00 -> 0b00 - expected_fprs[13] = fprs[5] # 0b10 -> 0b01 - expected_fprs[14] = fprs[6] # 0b01 -> 0b10 - expected_fprs[15] = fprs[7] # 0b11 -> 0b11 + expected_fprs[12] = fprs[4] # 0b00 -> 0b00 + expected_fprs[13] = fprs[5] # 0b10 -> 0b01 + expected_fprs[14] = fprs[6] # 0b01 -> 0b10 + expected_fprs[15] = fprs[7] # 0b11 -> 0b11 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_fprs=fprs) + initial_fprs=fprs) mem = sim.mem.dump(printout=False) - print ("mem dump") - print (mem) + print("mem dump") + print(mem) - print ("FPRs") + print("FPRs") sim.fpr.dump() - #self.assertEqual(mem, [(16, 0x020200000101), + # self.assertEqual(mem, [(16, 0x020200000101), # (24, 0x040400000303)]) self._check_fpregs(sim, expected_fprs) @@ -490,18 +489,18 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 12 # VL - svstate.maxvl = 12 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 12 # VL + svstate.maxvl = 12 # MAXVL + print("SVSTATE", bin(svstate.asint())) regs = [0] * 64 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_regs=regs) + initial_regs=regs) mem = sim.mem.dump(printout=False) - print ("Mem") - print (mem) + print("Mem") + print(mem) self.assertEqual(mem, [(16, 0x020200000101), (24, 0x040400000303), @@ -577,9 +576,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 8 # VL - svstate.maxvl = 8 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 8 # VL + svstate.maxvl = 8 # MAXVL + print("SVSTATE", bin(svstate.asint())) regs = [0] * 64 @@ -593,10 +592,10 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_regs=regs) + initial_regs=regs) mem = sim.mem.dump(printout=False) - print ("Mem") - print (mem) + print("Mem") + print(mem) self.assertEqual(mem, [(16, 0x010200000001), (24, 0x030400000203), @@ -604,13 +603,13 @@ class DecoderTestCase(FHDLTestCase): (40, 0x070800000607)]) # from STs for i in range(len(avi)): - print ("st gpr", i, sim.gpr(i+4), hex(avi[i])) + print("st gpr", i, sim.gpr(i+4), hex(avi[i])) for i in range(len(avi)): self.assertEqual(sim.gpr(i+4), avi[i]) # combination of bit-reversed load with a DCT half-swap REMAP # schedule for i in range(len(avi)): - print ("ld gpr", i, sim.gpr(i+12), hex(av[i])) + print("ld gpr", i, sim.gpr(i+12), hex(av[i])) for i in range(len(avi)): self.assertEqual(sim.gpr(i+12), av[i]) @@ -664,9 +663,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=4) svstate = SVP64State() - svstate.vl = 8 # VL - svstate.maxvl = 8 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 8 # VL + svstate.maxvl = 8 # MAXVL + print("SVSTATE", bin(svstate.asint())) regs = [0] * 64 @@ -680,10 +679,10 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_regs=regs) + initial_regs=regs) mem = sim.mem.dump(printout=False) - print ("Mem") - print (mem) + print("Mem") + print(mem) self.assertEqual(mem, [(16, 0x010200000001), (24, 0x030400000203), @@ -691,29 +690,29 @@ class DecoderTestCase(FHDLTestCase): (40, 0x070800000607)]) # from STs for i in range(len(avi)): - print ("st gpr", i, sim.gpr(i+4), hex(avi[i])) + print("st gpr", i, sim.gpr(i+4), hex(avi[i])) for i in range(len(avi)): self.assertEqual(sim.gpr(i+4), avi[i]) # combination of bit-reversed load with a DCT half-swap REMAP # schedule for i in range(len(avi)): - print ("ld gpr", i, sim.gpr(i+12), hex(av[i])) + print("ld gpr", i, sim.gpr(i+12), hex(av[i])) for i in range(len(avi)): self.assertEqual(sim.gpr(i+12), av[i]) def run_tst_program(self, prog, initial_regs=None, - svstate=None, initial_fprs=None, - initial_mem=None): + svstate=None, initial_fprs=None, + initial_mem=None): if initial_regs is None: initial_regs = [0] * 32 if initial_fprs is None: initial_fprs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate, - initial_fprs=initial_fprs, - mem=initial_mem) - print ("GPRs") + initial_fprs=initial_fprs, + mem=initial_mem) + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_logical.py b/src/openpower/decoder/isa/test_caller_svp64_logical.py index b98ebeb3..40246e99 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_logical.py +++ b/src/openpower/decoder/isa/test_caller_svp64_logical.py @@ -6,8 +6,9 @@ related bugs: """ import unittest -from openpower.test.runner import TestRunnerBase + from openpower.test.logical.svp64_cases import SVP64LogicalTestCase +from openpower.test.runner import TestRunnerBase # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py index 6c6f751b..dbca7847 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py @@ -1,19 +1,12 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class DecoderTestCase(FHDLTestCase): @@ -32,9 +25,9 @@ class DecoderTestCase(FHDLTestCase): * 1 = 6 + 1 => 0x303 + 0x404 => 0x707 """ isa = SVP64Asm(['sv.add/mr 1, *5, 1' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -43,9 +36,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x0404 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) # r1 = r1 + r5 + r6 @@ -54,7 +47,7 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, - svstate=svstate) + svstate=svstate) self._check_regs(sim, expected_regs) def test_sv_add_prefix_sum(self): @@ -68,9 +61,9 @@ class DecoderTestCase(FHDLTestCase): pascal's triangle! """ isa = SVP64Asm(['sv.add/mr *2, *2, *1' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -80,20 +73,20 @@ class DecoderTestCase(FHDLTestCase): initial_regs[4] = 0x4 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) for i in range(3): - print ("%d += %d" % (2+i, 1+i)) + print("%d += %d" % (2+i, 1+i)) expected_regs[2+i] += expected_regs[1+i] for i in range(5): - print ("expected", i, expected_regs[i]) + print("expected", i, expected_regs[i]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, - svstate=svstate) + svstate=svstate) self._check_regs(sim, expected_regs) def test_sv_add_prefix_sum_reverse(self): @@ -105,9 +98,9 @@ class DecoderTestCase(FHDLTestCase): * 2 = 2 + 1 => 3 + 4 => 7 """ isa = SVP64Asm(['sv.add/mrr *2, *2, *1' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -117,21 +110,21 @@ class DecoderTestCase(FHDLTestCase): initial_regs[4] = 0x1 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running, then compute answers expected_regs = deepcopy(initial_regs) for i in range(3): j = 2-i - print ("%d += %d" % (2+j, 1+j)) + print("%d += %d" % (2+j, 1+j)) expected_regs[2+j] += expected_regs[1+j] for i in range(5): - print ("expected", i, expected_regs[i]) + print("expected", i, expected_regs[i]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, - svstate=svstate) + svstate=svstate) self._check_regs(sim, expected_regs) def test_fp_muls_reduce(self): @@ -146,9 +139,9 @@ class DecoderTestCase(FHDLTestCase): * FPR 1 multiplied by FPR 4, 2.0 """ isa = SVP64Asm(["sv.fmuls/mr 1, *2, 1", - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) fprs = [0] * 32 fprs[1] = 0x401C000000000000 # 7.0 @@ -158,13 +151,13 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 3 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 3 # VL + svstate.maxvl = 3 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, - initial_fprs=fprs) + initial_fprs=fprs) # answer should be 7.0 * -9.8 * -9.8 * 2.0 = 1344.56 self.assertEqual(sim.fpr(1), SelectableInt(0x4095023d20000000, 64)) # these should not have been changed @@ -185,14 +178,14 @@ class DecoderTestCase(FHDLTestCase): fprs[2] = 0x401C000000000000 # 7.0 fprs[3] = 0xC02399999999999A # -9.8 fprs[4] = 0x4000000000000000 # 2.0 - fprs[5] = 0xC040266660000000 # -32.3 + fprs[5] = 0xC040266660000000 # -32.3 fprs[6] = 0x4000000000000000 # 2.0 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate, @@ -200,16 +193,16 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.fpr(6), SelectableInt(0x4074c8a3c0000000, 64)) def run_tst_program(self, prog, initial_regs=None, svstate=None, - initial_mem=None, - initial_fprs=None): + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) - print ("GPRs") + initial_fprs=initial_fprs, + svstate=svstate) + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index e77877de..0796e7c9 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -1,22 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase +import operator import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State +from functools import reduce + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.helpers import fp64toselectable +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy -from openpower.decoder.helpers import fp64toselectable -from functools import reduce -import operator class DecoderTestCase(FHDLTestCase): @@ -42,52 +33,51 @@ class DecoderTestCase(FHDLTestCase): # 3x2 matrix X1 = [[1, 2, 3], [3, 4, 5], - ] + ] # 2x3 matrix Y1 = [[6, 7], [8, 9], [10, 11], - ] + ] X = X1 Y = Y1 xf = reduce(operator.add, X) yf = reduce(operator.add, Y) - print ("flattened X,Y") - print ("\t", xf) - print ("\t", yf) + print("flattened X,Y") + print("\t", xf) + print("\t", yf) # and create a linear result2, same scheme #result1 = [0] * (ydim1*xdim2) - res = [] # store FPs for i, x in enumerate(xf): fprs[i+16] = fp64toselectable(float(x)) # X matrix for i, y in enumerate(yf): - fprs[i+32] = fp64toselectable(float(y)) # Y matrix + fprs[i+32] = fp64toselectable(float(y)) # Y matrix continue - #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single - #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double + # t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single + # u = DOUBLE2SINGLE(fp64toselectable(u)) # from double #res.append((t, u)) - #print ("FFT", i, "in", a, b, "coeff", c, "mul", + # print ("FFT", i, "in", a, b, "coeff", c, "mul", # mul, "res", t, u) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(4): - print ("i", i, float(sim.fpr(i))) + print("i", i, float(sim.fpr(i))) # confirm that the results are as expected - #for i, (t, u) in enumerate(res): + # for i, (t, u) in enumerate(res): # self.assertEqual(sim.fpr(i+2), t) # self.assertEqual(sim.fpr(i+6), u) @@ -107,34 +97,34 @@ class DecoderTestCase(FHDLTestCase): # 3x2 matrix X1 = [[1, 2, 3], [3, 4, 5], - ] + ] # 2x3 matrix Y1 = [[6, 7], [8, 9], [10, 11], - ] + ] - #### test matrices 2 + # test matrices 2 # 3x3 matrix - X2 = [[12,7,3], - [4 ,5,6], - [7 ,8,9], - ] + X2 = [[12, 7, 3], + [4, 5, 6], + [7, 8, 9], + ] # 3x4 matrix - Y2 = [[5,8,1,2], - [6,7,3,0], - [4,5,9,1]] + Y2 = [[5, 8, 1, 2], + [6, 7, 3, 0], + [4, 5, 9, 1]] - #### test matrices 3 + # test matrices 3 # 3x4 matrix - X3 = [[12,7,3], - [4 ,5,6], - [7 ,8,9], - [2 ,0,1]] + X3 = [[12, 7, 3], + [4, 5, 6], + [7, 8, 9], + [2, 0, 1]] # 3x5 matrix - Y3 = [[5,8,1,2,3], - [6,7,3,0,9], - [4,5,9,1,2]] + Y3 = [[5, 8, 1, 2, 3], + [6, 7, 3, 0, 9], + [4, 5, 9, 1, 2]] X = X2 Y = Y2 @@ -145,45 +135,44 @@ class DecoderTestCase(FHDLTestCase): xdim2 = len(Y[0]) ydim2 = len(Y) - print ("xdim2 ydim1 ydim2", xdim2, ydim1, ydim2) + print("xdim2 ydim1 ydim2", xdim2, ydim1, ydim2) xf = reduce(operator.add, X) yf = reduce(operator.add, Y) - print ("flattened X,Y") - print ("\t", xf) - print ("\t", yf) + print("flattened X,Y") + print("\t", xf) + print("\t", yf) # and create a linear result2, same scheme #result1 = [0] * (ydim1*xdim2) - res = [] # store FPs fprs = [0] * 64 for i, x in enumerate(xf): fprs[i+16] = fp64toselectable(float(x)) # X matrix for i, y in enumerate(yf): - fprs[i+32] = fp64toselectable(float(y)) # Y matrix + fprs[i+32] = fp64toselectable(float(y)) # Y matrix continue - #t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single - #u = DOUBLE2SINGLE(fp64toselectable(u)) # from double + # t = DOUBLE2SINGLE(fp64toselectable(t)) # convert to Power single + # u = DOUBLE2SINGLE(fp64toselectable(u)) # from double #res.append((t, u)) - #print ("FFT", i, "in", a, b, "coeff", c, "mul", + # print ("FFT", i, "in", a, b, "coeff", c, "mul", # mul, "res", t, u) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(16): - print ("i", i, float(sim.fpr(i))) + print("i", i, float(sim.fpr(i))) # confirm that the results are as expected - #for i, (t, u) in enumerate(res): + # for i, (t, u) in enumerate(res): # self.assertEqual(sim.fpr(i+2), t) # self.assertEqual(sim.fpr(i+6), u) @@ -211,11 +200,11 @@ class DecoderTestCase(FHDLTestCase): """ # 3x4 matrix of data to be ORed together by row. # Add any number of extra rows (up to 6) here (6 because sv.or *0,*0,*6) - X1 = [[0x1, 0x10, 0x100], # 0x111 - [0x2, 0x40, 0x300], # 0x342 - [0x9, 0x70, 0x800], # 0x879 - [0x3, 0x71, 0x460], # overlaps (still ORed) - 0x473 - ] + X1 = [[0x1, 0x10, 0x100], # 0x111 + [0x2, 0x40, 0x300], # 0x342 + [0x9, 0x70, 0x800], # 0x879 + [0x3, 0x71, 0x460], # overlaps (still ORed) - 0x473 + ] # get the dimensions of the array xdim1 = len(X1[0]) @@ -230,15 +219,15 @@ class DecoderTestCase(FHDLTestCase): ]) lst = list(lst) - print ("xdim1, ydim1", xdim1, ydim1) + print("xdim1, ydim1", xdim1, ydim1) expected = [0] * ydim1 for i, row in enumerate(X1): expected[i] = reduce(operator.or_, row) - print ("\texpected ORed", hex(expected[i])) + print("\texpected ORed", hex(expected[i])) xf = reduce(operator.add, X1) - print ("flattened X") - print ("\t", xf) + print("flattened X") + print("\t", xf) res = [] # store FPs @@ -248,31 +237,31 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, gprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(ydim1): - print ("i", i, sim.gpr(0+i), hex(expected[i])) + print("i", i, sim.gpr(0+i), hex(expected[i])) for i in range(ydim1): self.assertEqual(sim.gpr(0+i), SelectableInt(expected[i], 64)) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py index b80ec5dc..e3edd216 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pack.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py @@ -1,24 +1,17 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import CRFields, SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy + class DecoderTestCase(FHDLTestCase): def _check_regs(self, sim, expected): - print ("GPR") + print("GPR") sim.gpr.dump() for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) @@ -28,27 +21,27 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", "svstep 0, 15, 0", # set dst-pack - "sv.svstep./vec2 *0, 5, 1", # svstep get vector srcstep - "sv.svstep./vec2 *8, 6, 1", # svstep get vector dststep - "sv.svstep./vec2 *16, 7, 1", # svstep get src substep - "sv.svstep./vec2 *24, 8, 1", # svstep get dst substep + "sv.svstep./vec2 *0, 5, 1", # svstep get vector srcstep + "sv.svstep./vec2 *8, 6, 1", # svstep get vector dststep + "sv.svstep./vec2 *16, 7, 1", # svstep get src substep + "sv.svstep./vec2 *24, 8, 1", # svstep get dst substep ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) sim.gpr.dump() self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) @@ -78,15 +71,15 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", "svstep 0, 14, 0", # set src-pack - "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order + "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0]*64 for i in range(8): @@ -94,12 +87,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) sim.gpr.dump() self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) @@ -116,15 +109,15 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", "svstep 0, 15, 0", # set dst-pack - "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order + "sv.ori/vec2 *0, *32, 0", # copy 01234567 to new order ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) initial_regs = [0]*64 for i in range(8): @@ -132,12 +125,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) sim.gpr.dump() self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) @@ -160,9 +153,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) mask = 0b0110 initial_regs = [0xffffffff]*64 @@ -172,12 +165,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) sim.gpr.dump() self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) @@ -191,19 +184,19 @@ class DecoderTestCase(FHDLTestCase): for i in range(4): offs = j*4+i skew = i*2+j - if mask & (1<<(skew>>1)): + if mask & (1 << (skew >> 1)): to_expect.append(skew) - print ("expected", to_expect) + print("expected", to_expect) for j in range(2): for i in range(4): offs = j*4+i skew = i*2+j - if mask & (1<<(offs>>1)): + if mask & (1 << (offs >> 1)): expected = SelectableInt(to_expect.pop(0), 64) else: expected = SelectableInt(0xffffffff, 64) - print ("checking", hex(expected.value), "at", offs) + print("checking", hex(expected.value), "at", offs) self.assertEqual(sim.gpr(8+offs), expected) def test_svstep_unpack(self): @@ -211,15 +204,15 @@ class DecoderTestCase(FHDLTestCase): """ lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", "svstep 0, 14, 0", # set src-pack - "sv.ori/vec2/m=r3 *8, *16, 0", # copy with mask + "sv.ori/vec2/m=r3 *8, *16, 0", # copy with mask ]) lst = list(lst) # SVSTATE svstate = SVP64State() - #svstate.vl = 2 # VL - #svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + # svstate.vl = 2 # VL + # svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) mask = 0b0101 initial_regs = [0xffffffff]*64 @@ -229,12 +222,12 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" vfirst", bin(sim.svstate. vfirst)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" vfirst", bin(sim.svstate. vfirst)) sim.gpr.dump() self.assertEqual(sim.svstate.vl, 4) self.assertEqual(sim.svstate.maxvl, 4) @@ -248,31 +241,30 @@ class DecoderTestCase(FHDLTestCase): for i in range(4): offs = j*4+i skew = i*2+j - if mask & (1<<(offs>>1)): + if mask & (1 << (offs >> 1)): to_expect.append(offs) - print ("expected", to_expect) + print("expected", to_expect) for j in range(2): for i in range(4): offs = j*4+i skew = i*2+j - if mask & (1<<(skew>>1)): + if mask & (1 << (skew >> 1)): expected = SelectableInt(to_expect.pop(0), 64) else: expected = SelectableInt(0xffffffff, 64) self.assertEqual(sim.gpr(8+skew), expected) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_sprs=None): + svstate=None, + initial_sprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate, - initial_sprs=initial_sprs) + initial_sprs=initial_sprs) simulator.gpr.dump() return simulator if __name__ == "__main__": unittest.main() - diff --git a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py index 14a67026..831a6353 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py +++ b/src/openpower/decoder/isa/test_caller_svp64_parallel_reduce.py @@ -1,23 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase +import operator import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State -from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst -from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase from openpower.decoder.helpers import fp64toselectable from openpower.decoder.isa.remap_preduce_yield import preduce_y -from functools import reduce -import operator +from openpower.decoder.isa.test_caller import run_tst +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.sv.trans.svp64 import SVP64Asm def signcopy(x, y): @@ -56,17 +46,17 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(7): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected expected = preduce_y(vec) for i, v in enumerate(res): @@ -96,22 +86,22 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs=gprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) for i in range(7): val = sim.gpr(i).value res.append(val) - print ("i", i, val) + print("i", i, val) # confirm that the results are as expected, mask with 64-bit expected = preduce_y(vec, operation=operator.sub) for i, v in enumerate(res): - self.assertEqual(v&0xffffffffffffffff, - expected[i]&0xffffffffffffffff) + self.assertEqual(v & 0xffffffffffffffff, + expected[i] & 0xffffffffffffffff) def test_sv_remap3(self): """>>> lst = ["svshape 7, 0, 0, 7, 0", @@ -137,36 +127,36 @@ class DecoderTestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_fprs=fprs) - print ("spr svshape0", sim.spr['SVSHAPE0']) - print (" xdimsz", sim.spr['SVSHAPE0'].xdimsz) - print (" ydimsz", sim.spr['SVSHAPE0'].ydimsz) - print (" zdimsz", sim.spr['SVSHAPE0'].zdimsz) - print ("spr svshape1", sim.spr['SVSHAPE1']) - print ("spr svshape2", sim.spr['SVSHAPE2']) - print ("spr svshape3", sim.spr['SVSHAPE3']) + print("spr svshape0", sim.spr['SVSHAPE0']) + print(" xdimsz", sim.spr['SVSHAPE0'].xdimsz) + print(" ydimsz", sim.spr['SVSHAPE0'].ydimsz) + print(" zdimsz", sim.spr['SVSHAPE0'].zdimsz) + print("spr svshape1", sim.spr['SVSHAPE1']) + print("spr svshape2", sim.spr['SVSHAPE2']) + print("spr svshape3", sim.spr['SVSHAPE3']) # confirm that the results are as expected expected = preduce_y(vec, operation=signcopy) for i in range(7): val = sim.fpr(i).value res.append(val) - print ("i", i, float(sim.fpr(i)), vec[i], expected[i]) + print("i", i, float(sim.fpr(i)), vec[i], expected[i]) for i, v in enumerate(res): - self.assertEqual(v&0xffffffffffffffff, + self.assertEqual(v & 0xffffffffffffffff, fp64toselectable(expected[i]).value) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_mem=None, - initial_fprs=None): + svstate=None, + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs, - svstate=svstate) + initial_fprs=initial_fprs, + svstate=svstate) - print ("GPRs") + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index ba6906b4..a0552e75 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -1,27 +1,21 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import CRFields, SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy + class DecoderTestCase(FHDLTestCase): def _check_regs(self, sim, expected): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64), - "reg %d expected %x got %x" % \ - (i, sim.gpr(i).value, expected[i])) + "reg %d expected %x got %x" % + (i, sim.gpr(i).value, expected[i])) def tst_sv_load_store(self): lst = SVP64Asm(["addi 1, 0, 0x0010", @@ -34,9 +28,9 @@ class DecoderTestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, svstate=svstate) @@ -67,9 +61,9 @@ class DecoderTestCase(FHDLTestCase): # dest r3=0b10 N Y isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -78,13 +72,13 @@ class DecoderTestCase(FHDLTestCase): initial_regs[10] = 0x90 # this gets skipped # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[5] = 0x0 # dest r3 is 0b10: skip - expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1 + expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1 with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate) @@ -93,25 +87,25 @@ class DecoderTestCase(FHDLTestCase): def test_sv_extsw_intpred_dz(self): # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest isa = SVP64Asm(['sv.extsb/dm=r3/dz *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 initial_regs[3] = 0b01 # predicate mask (dest) - initial_regs[5] = 0xfeed # going to be overwritten - initial_regs[6] = 0xbeef # going to be overwritten (with zero) + initial_regs[5] = 0xfeed # going to be overwritten + initial_regs[6] = 0xbeef # going to be overwritten (with zero) initial_regs[9] = 0x91 # dest r3 is 0b01 so this will be used initial_regs[10] = 0x90 # this gets read but the output gets zero'd # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) - expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store + expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store expected_regs[6] = 0 # 2nd bit of r3 is 1: zero with Program(lst, bigendian=False) as program: @@ -130,9 +124,9 @@ class DecoderTestCase(FHDLTestCase): # | | # dest r3=0b10 N Y isa = SVP64Asm(['sv.add/m=r3 *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -144,9 +138,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = 0xbeef @@ -161,9 +155,9 @@ class DecoderTestCase(FHDLTestCase): # 1 = 5 + 9 => not to be touched (skipped) # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 isa = SVP64Asm(['sv.add/m=ne *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -174,16 +168,16 @@ class DecoderTestCase(FHDLTestCase): initial_regs[6] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[1] = 0xbeef expected_regs[2] = 0x3334 # set up CR predicate - CR4.eq=1 and CR5.eq=0 - cr = (0b0010) << ((7-4)*4) # CR4.eq (we hope) + cr = (0b0010) << ((7-4)*4) # CR4.eq (we hope) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate, @@ -457,8 +451,8 @@ class DecoderTestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_cr=0): + svstate=None, + initial_cr=0): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_subvl.py b/src/openpower/decoder/isa/test_caller_svp64_subvl.py index 3707de98..01f1232e 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_subvl.py +++ b/src/openpower/decoder/isa/test_caller_svp64_subvl.py @@ -1,19 +1,13 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy + class DecoderTestCase(FHDLTestCase): @@ -33,16 +27,16 @@ class DecoderTestCase(FHDLTestCase): # | | | | # dest r3=0b10 N N Y Y isa = SVP64Asm(['sv.add/vec2/m=r30 *1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 initial_regs[1] = 0xbeef # not to be altered initial_regs[2] = 0xefbe # not to be altered - initial_regs[3] = 0xebbe - initial_regs[4] = 0xbeeb + initial_regs[3] = 0xebbe + initial_regs[4] = 0xbeeb initial_regs[30] = 0b10 # predicate mask initial_regs[9] = 0x1234 initial_regs[10] = 0x1111 @@ -54,9 +48,9 @@ class DecoderTestCase(FHDLTestCase): initial_regs[8] = 0x2223 # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) expected_regs[3] = initial_regs[7]+initial_regs[11] @@ -66,10 +60,9 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) - def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_cr=0): + svstate=None, + initial_cr=0): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate, diff --git a/src/openpower/decoder/isa/test_caller_svp64_utf_8_validation.py b/src/openpower/decoder/isa/test_caller_svp64_utf_8_validation.py index 9c0ac839..83dc5ea4 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_utf_8_validation.py +++ b/src/openpower/decoder/isa/test_caller_svp64_utf_8_validation.py @@ -2,10 +2,11 @@ # Copyright 2022 Jacob Lifshay import unittest +from functools import lru_cache + from openpower.test.algorithms.svp64_utf_8_validation import \ SVP64UTF8ValidationTestCase from openpower.test.runner import TestRunnerBase -from functools import lru_cache # writing the test_caller invocation this way makes it work with pytest diff --git a/src/openpower/decoder/isa/test_caller_svshape2.py b/src/openpower/decoder/isa/test_caller_svshape2.py index fc92c80d..53ae23c9 100644 --- a/src/openpower/decoder/isa/test_caller_svshape2.py +++ b/src/openpower/decoder/isa/test_caller_svshape2.py @@ -1,22 +1,15 @@ """SVP64 unit test for svshape2 svshape2 SVo,yx,rmm,SVd,sk,mm """ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class SVSTATETestCase(FHDLTestCase): @@ -106,7 +99,7 @@ class SVSTATETestCase(FHDLTestCase): set the offset to compensate for EXTRA2 being so restricted. """ # set some parameters here with comments - offs = 1 # an offset of 1 + offs = 1 # an offset of 1 mod = 3 # modulo 3 on the range VL = 6 # RB will go 0..5 but RA will go 1 2 3 1 2 3 isa = SVP64Asm(['svshape2 %d, 0, 1, %d, 0, 0' % (offs, mod), diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index bfc7a5b6..c8ef62c3 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -1,27 +1,19 @@ """SVP64 unit test for doing strange things to SVSTATE, manually. """ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from copy import deepcopy + +from nmutil.formaltest import FHDLTestCase +from openpower.decoder.isa.caller import CRFields, SVP64State +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.simulator.program import Program from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy class SVSTATETestCase(FHDLTestCase): - def _check_regs(self, sim, expected): - print ("GPR") + print("GPR") sim.gpr.dump() for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) @@ -36,9 +28,9 @@ class SVSTATETestCase(FHDLTestCase): the Scalar one is NOT moved on. """ isa = SVP64Asm(['sv.add 1, *5, *9' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -49,11 +41,11 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE (in this case, VL=3, and src/dststep set ALREADY to 1) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - svstate.srcstep = 1 # srcstep - svstate.dststep = 1 # srcstep - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + svstate.srcstep = 1 # srcstep + svstate.dststep = 1 # srcstep + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -109,9 +101,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE (in this case, VL=2) svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print("SVSTATE", bin(svstate.asint())) # initial values in GPR regfile initial_regs = [0] * 32 @@ -128,18 +120,18 @@ class SVSTATETestCase(FHDLTestCase): with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) self.assertEqual(sim.svstate.vl, 2) self.assertEqual(sim.svstate.maxvl, 2) self.assertEqual(sim.svstate.srcstep, 0) self.assertEqual(sim.svstate.dststep, 0) # when end reached, vertical mode is exited - print(" msr", bin(sim.msr.value)) # should be zero - self.assertEqual(sim.msr, SelectableInt(0<<(63-6), 64)) + print(" msr", bin(sim.msr.value)) # should be zero + self.assertEqual(sim.msr, SelectableInt(0 << (63-6), 64)) CR0 = sim.crl[0] print(" CR0", bin(CR0.get_range().value)) self.assertEqual(CR0[CRFields.EQ], 0) @@ -151,7 +143,7 @@ class SVSTATETestCase(FHDLTestCase): self._check_regs(sim, expected_regs) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate) @@ -161,4 +153,3 @@ class SVSTATETestCase(FHDLTestCase): if __name__ == "__main__": unittest.main() - diff --git a/src/openpower/decoder/isa/test_caller_transcendentals.py b/src/openpower/decoder/isa/test_caller_transcendentals.py index 08488bfb..306ab1f6 100644 --- a/src/openpower/decoder/isa/test_caller_transcendentals.py +++ b/src/openpower/decoder/isa/test_caller_transcendentals.py @@ -1,30 +1,20 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase +import math import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State -from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst -from copy import deepcopy -from openpower.sv.trans.svp64 import SVP64Asm + +from nmutil.formaltest import FHDLTestCase from openpower.decoder.helpers import fp64toselectable +from openpower.decoder.isa.test_caller import run_tst from openpower.decoder.isafunctions.double2single import ISACallerFnHelper +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.sv.trans.svp64 import SVP64Asm # really bad hack. need to access the DOUBLE2SINGLE function auto-generated # from pseudo-code. fph = ISACallerFnHelper(XLEN=64) -import math - class FPTranscendentalsTestCase(FHDLTestCase): - def _check_regs(self, sim, expected_int, expected_fpr): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) @@ -38,7 +28,7 @@ class FPTranscendentalsTestCase(FHDLTestCase): """ lst = SVP64Asm(["fsins 1, 2", "fcoss 3, 2", - ]) + ]) lst = list(lst) with Program(lst, bigendian=False) as program: @@ -48,9 +38,9 @@ class FPTranscendentalsTestCase(FHDLTestCase): fprs[2] = fp64toselectable(a) t = math.sin(a) u = math.cos(a) - a1 = fp64toselectable(a) # convert to Power single - t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # to Power single - u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single + a1 = fp64toselectable(a) # convert to Power single + t = fph.DOUBLE2SINGLE(fp64toselectable(t)) # to Power single + u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single with self.subTest(): sim = self.run_tst_program(program, initial_fprs=fprs) @@ -73,11 +63,11 @@ class FPTranscendentalsTestCase(FHDLTestCase): lst = SVP64Asm(["std 1, 0(0)", "lfd 0, 0(0)", "fcfids 0, 0", - "fadds 0, 0, 3", # plus 0.5 - "fmuls 0, 0, 1", # times PI - "fdivs 0, 0, 2", # div 4.0 + "fadds 0, 0, 3", # plus 0.5 + "fmuls 0, 0, 1", # times PI + "fdivs 0, 0, 2", # div 4.0 "fcoss 4, 0", - ]) + ]) lst = list(lst) with Program(lst, bigendian=False) as program: @@ -85,19 +75,20 @@ class FPTranscendentalsTestCase(FHDLTestCase): fprs = [0] * 32 # constants fprs[3] = fp64toselectable(0.5) # 0.5 - fprs[1] = fp64toselectable(math.pi) # pi + fprs[1] = fp64toselectable(math.pi) # pi fprs[2] = fp64toselectable(4.0) # 4.0 - #for i in range(-8, 9): + # for i in range(-8, 9): for i in range(7, 8): a = math.pi * ((i+0.5) / 4.0) gprs[1] = i - a1 = fph.DOUBLE2SINGLE(fp64toselectable(a)) # to Power single + a1 = fph.DOUBLE2SINGLE(fp64toselectable(a)) # to Power single a = float(a1) u = math.cos(a) - u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single + u = fph.DOUBLE2SINGLE(fp64toselectable(u)) # to Power single with self.subTest(): - sim = self.run_tst_program(program, gprs, initial_fprs=fprs) + sim = self.run_tst_program( + program, gprs, initial_fprs=fprs) print("FPR 0", sim.fpr(0), float(sim.fpr(0))) print("FPR 1", sim.fpr(1), float(sim.fpr(1))) print("FPR 2", sim.fpr(2), float(sim.fpr(2))) @@ -106,23 +97,23 @@ class FPTranscendentalsTestCase(FHDLTestCase): # sign should not do this, but hey actual_r = float(sim.fpr(0)) expected_r = float(a1) - err = abs(actual_r - expected_r ) / expected_r + err = abs(actual_r - expected_r) / expected_r self.assertTrue(err < 1e-6) actual_r = float(sim.fpr(4)) expected_r = float(u) - err = abs(actual_r - expected_r ) / expected_r + err = abs(actual_r - expected_r) / expected_r self.assertTrue(err < 1e-6) def run_tst_program(self, prog, initial_regs=None, - initial_mem=None, - initial_fprs=None): + initial_mem=None, + initial_fprs=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, mem=initial_mem, - initial_fprs=initial_fprs) - print ("GPRs") + initial_fprs=initial_fprs) + print("GPRs") simulator.gpr.dump() - print ("FPRs") + print("FPRs") simulator.fpr.dump() return simulator -- 2.30.2