From e83ac064486bbd0cea637551fdd1acf674468532 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 11 Apr 2022 18:49:55 +0100
Subject: [PATCH] fix coldboot to boot from return address (head.S does mtctr
 %r3 then bctr) move SPI offset to 6 mbytes (make room in future for boot
 bitstream) crank versa_ecp5 freq back to 55 mhz so as to re-activate DDR3

---
 coldboot/coldboot.c | 11 +++++++++++
 coldboot/head.S     |  4 ++++
 src/ls2.py          |  6 +++---
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index d725c83..b48b6ef 100644
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -11,6 +11,11 @@
 
 #include "elf64.h"
 
+static inline void mtspr(int sprnum, unsigned long val)
+{
+    __asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val));
+}
+
 static inline uint32_t read32(const void *addr)
 {
 	return *(volatile uint32_t *)addr;
@@ -485,6 +490,12 @@ int main(void) {
         unsigned long faddr = copy_flash(spi_offs);
         if (faddr != -1ul) {
             // jump to absolute address
+            /* could do it this way but hey modify head.S instead
+               mtspr(8, faddr); // move address to LR
+               __asm__ volatile("blr");
+            */
+
+            // works with head.S which copies r3 into ctr then does bctr
             return faddr;
         }
     }
diff --git a/coldboot/head.S b/coldboot/head.S
index 38d5421..d5b93dd 100644
--- a/coldboot/head.S
+++ b/coldboot/head.S
@@ -63,6 +63,10 @@ boot_entry:
 	LOAD_IMM64(%r12, main)
 	mtctr	%r12,
 	bctrl
+    /* move return result to ctr and branch to it */
+    mtctr   %r3
+    bctr
+    /* infinite loop */
 	b .
 
 #define EXCEPTION(nr)		\
diff --git a/src/ls2.py b/src/ls2.py
index 0d11514..332e3d1 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -317,8 +317,8 @@ class DDR3SoC(SoC, Elaboratable):
             self._decoder.add(self.bootmem.bus, addr=fw_addr) # ROM at fw_addr
 
         # System Configuration info
-        # offset executable ELF payload at 1 megabyte offset (1<<20)
-        spi_offset = 1<<20 if (spi_0_pins is not None) else None
+        # offset executable ELF payload at 6 megabyte offset (6<<20)
+        spi_offset = 6<<20 if (spi_0_pins is not None) else None
         dram_offset = ddr_addr if (ddr_pins is not None) else None
         self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq,
                                       has_uart=(uart_pins is not None),
@@ -662,7 +662,7 @@ def build_platform(fpga, firmware):
     if fpga == 'isim':
         clk_freq = 55e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
-        clk_freq = 45e6 # crank right down to test hyperram
+        clk_freq = 55e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
         # 50MHz works.  100MHz works.  55MHz does NOT work.
         # Stick with multiples of 50MHz...
-- 
2.30.2