From e84bed4b66dcd68856aeb6aed028ccda31cbf5b5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 11 May 2021 12:27:00 +0100 Subject: [PATCH] add setting of MSR "PR" bit for when running MMU test --- src/openpower/test/mmu/mmu_rom_cases.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/mmu/mmu_rom_cases.py b/src/openpower/test/mmu/mmu_rom_cases.py index 75ba5617..746d8a10 100644 --- a/src/openpower/test/mmu/mmu_rom_cases.py +++ b/src/openpower/test/mmu/mmu_rom_cases.py @@ -1,6 +1,8 @@ from openpower.simulator.program import Program from openpower.endian import bigendian from openpower.test.common import (TestAccumulatorBase, skip_case) +from openpower.consts import MSR + def b(x): return int.from_bytes(x.to_bytes(8, byteorder='little'), @@ -45,9 +47,11 @@ class MMUTestCaseROM(TestAccumulatorBase): prtbl = 0x1000000 initial_regs[1] = prtbl + initial_msr = 1 << MSR.PR # must set "problem" state for virtual memory initial_sprs = {'DSISR': 0, 'DAR': 0, 720: 0} self.add_case(Program(lst, bigendian), - initial_regs, initial_sprs) + initial_regs, initial_sprs, + initial_msr=initial_msr) -- 2.30.2