From e853ad4b616efc4ee80f3913a2a316a7f0c94fd3 Mon Sep 17 00:00:00 2001 From: David Jablonski Date: Sun, 24 May 2020 16:12:07 +0200 Subject: [PATCH] fix uart startbit: 1 cycle later --- litex/soc/cores/uart.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 07fdac30..eafbe6c0 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -99,8 +99,7 @@ class RS232PHYTX(Module): If(self.sink.valid & ~tx_busy & ~self.sink.ready, tx_reg.eq(self.sink.data), tx_bitcount.eq(0), - tx_busy.eq(1), - pads.tx.eq(0) + tx_busy.eq(1) ).Elif(uart_clk_txen & tx_busy, tx_bitcount.eq(tx_bitcount + 1), If(tx_bitcount == 8, @@ -113,6 +112,10 @@ class RS232PHYTX(Module): pads.tx.eq(tx_reg[0]), tx_reg.eq(Cat(tx_reg[1:], 0)) ) + ).Elif(tx_busy, + If(tx_bitcount == 0, + pads.tx.eq(0) + ) ) ] self.sync += [ @@ -235,7 +238,7 @@ class UART(Module, AutoCSR, UARTInterface): self._rxempty.status.eq(~rx_fifo.source.valid), self._rxtx.w.eq(rx_fifo.source.data), rx_fifo.source.ready.eq(self.ev.rx.clear | (rx_fifo_rx_we & self._rxtx.we)), - # Generate RX IRQ when tx_fifo becomes non-empty + # Generate RX IRQ when rx_fifo becomes non-empty self.ev.rx.trigger.eq(~rx_fifo.source.valid) ] -- 2.30.2