From e85a71de680326846b2a06bb61a394ac4815418a Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 9 Jun 2022 13:42:35 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 299d624f2..36c59d594 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -40,7 +40,7 @@ not fundamentally change an add operation into a subtract for example, and under absolutely no circumstances do the actual 32-bit Scalar v3.0 operand field bits change or the number of operands change. -*(In an early Draft of SVP64, +In an early Draft of SVP64, an experiment was attempted, to modify LD-immediate instructions to include a third RC register i.e. reinterpret the normal @@ -53,7 +53,14 @@ to add a 32-bit Scalar Load-with-Shift instruction *first*, which then inherently becomes Vectorised. Perhaps a future Power ISA spec will have this Load-with-Shift instruction: both ARM and x86 have it, because it saves greatly on instruction count in -hot-loops.)* +hot-loops. + +The other reason for not adding an SVP64-Prefixed instruction without +also having it as a Scalar un-prefixed instruction is that if the +32-bit encoding is ever allocated to a completely unrelated operation +then how can a Vectorised version of that new instruction ever be added? +Bottom line here is that the fundamental RISC Principle is strictly adhered +to, even though these are Advanced 64-bit Vector instructions. # Instruction Groups -- 2.30.2