From e86104d3a69afff91638686d3b57303f67c7c13d Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 16 Dec 2018 16:20:45 +0000 Subject: [PATCH] back.rtlil: use slicing to match shape when reducing width. --- nmigen/back/rtlil.py | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 05d4ac6..7f584ff 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -339,19 +339,19 @@ class _RHSValueCompiler(_ValueCompiler): return self(ast.Const(value.value, (new_bits, new_sign))) value_bits, value_sign = value.shape() - if new_bits > value_bits: - res = self.s.rtlil.wire(width=new_bits) - self.s.rtlil.cell("$pos", ports={ - "\\A": self(value), - "\\Y": res, - }, params={ - "A_SIGNED": value_sign, - "A_WIDTH": value_bits, - "Y_WIDTH": new_bits, - }, src=src(value.src_loc)) - return res - else: - return "{} [{}:0]".format(self(value), new_bits - 1) + if new_bits <= value_bits: + return self(ast.Slice(value, 0, new_bits)) + + res = self.s.rtlil.wire(width=new_bits) + self.s.rtlil.cell("$pos", ports={ + "\\A": self(value), + "\\Y": res, + }, params={ + "A_SIGNED": value_sign, + "A_WIDTH": value_bits, + "Y_WIDTH": new_bits, + }, src=src(value.src_loc)) + return res def on_Operator_binary(self, value): lhs, rhs = value.operands -- 2.30.2